BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /

Memory ICs

BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W

(10) Random read cycle

BR24C01A-W / AF-W / AFJ-W / AFV-W

S

T

O

P

A

C

K

R

E

A

D

DATA(n)

SLAVE

ADDRESS

SLAVE

ADDRESS

WORD

ADDRESS(n)

SDA

LINE

S

T

A

R

T

S

T

A

R

T

11

0

0 A2 A1 A0

R

/

W

R

/

W

A

C

K

A

C

K

A

C

K

W

R

I

T

E

11

0

0 A2 A1A0

D7

D0

Fig.13

∗

WA

6

WA

0

BR24C02-W / F-W / FJ-W / FV-W

S

T

O

P

A

C

K

R

E

A

D

DATA(n)

SLAVE

ADDRESS

SLAVE

ADDRESS

WORD

ADDRESS(n)

SDA

LINE

S

T

A

R

T

S

T

A

R

T

11

0

0 A2 A1A0

R

/

W

R

/

W

A

C

K

A

C

K

A

C

K

W

R

I

T

E

11

0

0 A2 A1 A0

D7

D0

Fig.14

WA

7

WA

0

BR24C04-W / F-W / FJ-W / FV-W

S

T

O

P

A

C

K

R

E

A

D

DATA(n)

SLAVE

ADDRESS

SLAVE

ADDRESS

WORD

ADDRESS(n)

SDA

LINE

S

T

A

R

T

S

T

A

R

T

11

0

0 A2 A1PS

R

/

W

R

/

W

A

C

K

A

C

K

A

C

K

WA

7

WA

0

W

R

I

T

E

11

0

0 A2 A1 PS

D7

D0

Fig.15

• This command can read the designated word address data.

• When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next

word address data can be read.

[All words all read enabled]

(See Fig.16 to 18 for the sequential read cycles.)

• This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop

condition) by raising SCL to HIGH.