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BR24C01AFJ-W Datasheet(PDF) 6 Page - Rohm |
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BR24C01AFJ-W Datasheet(HTML) 6 Page - Rohm |
6 / 13 page BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W When data is being read from the IC, eight bits of data (read data) are output and the IC waits for a returned LOW acknowledge signal (ACK signal). When an acknowledge signal (ACK signal) is detected and a stop condition is not sent from the master ( µ-COM) side, the IC continues to output data. If an acknowledge signal (ACK signal) is not detected, the IC interrupts the data transfer and ceases reading operations after recognizing the stop condition (stop bit). The IC then enters the waiting or standby state. (See Fig.3 for acknowledge signal (ACK signal) response.) 1 8 9 SCL SDA SDA Start condition (start bit) Acknowledge signal (ACK signal) (from µ-COM) ( µ-COM output data) (IC output data) Fig.3 Acknowledge (ACK signal) response (during write and read slave address input) (7) Byte write cycle BR24C01A-W / AF-W / AFJ-W / AFV-W 1 0 1 0 A2 A1 A0 D7 D0 S T O P DATA A C K A C K A C K WORD ADDRESS R / W W R I T E SLAVE ADDRESS S T A R T SDA LINE WP Fig.4 ∗ WA 6 WA 0 |
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