(1) Connect pin 1 to GND via a 120k

Ω (approx.) resistor. Leave pins 2, 4 and 8 open.

(2) SYNC output polarity (pin 3) is positive.

(3) The delay time for rising edge of the SYNC output (pin 3) with respect to the falling edge of Sync for the Vsig

input signal (pin 6) is 850ns (reference value).

(4) The delay time for falling edge of the SYNC output (pin 3) with respect to the rising edge of Sync for the Vsig

input signal (pin 6) is 450ns (reference value).

5

Multimedia ICs

BA7046 / BA7046F

8

8

7

6

5

470k

H. OSC

V. SEPA

PHASE

COMP

SYNC

SEPA

0.022

µ

47

µ

1

µ

1

µ

+

+

+

470k

330

10k

470k

Vsig

100p

130k

SYNC

10k

10k

1

2

3

4

0.47

µ

0.47

µ

2200p

∗

Fig.9

diagram on the right, you can decrease the lock-in time and increase the

capture range.

8

7

6

5

H. OSC

V. SEPA

PHASE

COMP

SYNC

SEPA

0.022

µ

47

µ

1

µ

+

+

470k

330

Vsig

120k

SYNC

10k

1

2

3

4

Fig. 10