Preliminary
2-49
RF2117
Rev A0 991201
2
Pin
Function
Description
Interface Schematic
1VREG
Regulated Supply for bias circuit. This pin should be connected to the
regulated supply with a ferrite of 240 ohms and should have a UHF
decoupling capacitor (100pF) to ground at the supply end of the ferrite.
An additional capacitor of 1nF can be added with the 100 pF but it’s
placement is not as critical.
2VCC1
Positive supply for the active bias circuits. Bypassing should be accom-
plished with a single UHF decoupling capacitor, placed close to the Pin.
Additional bypassing of 1nF is also recommended, but proximity to the
package is not as critical.
3LTUNE
The Inter-stage matching point of the amplifiers. Matching should be
performed with a small value inductor connected from the pin to
ground.
4Q1C
Positive Supply to the first stage collector. The supply should be fed
through a parallel LC network, resonant at the centre of the band of
interest. A UHF decoupling capacitor should be placed from the supply
end of the LC to ground. A 1nF capacitor can also be used but it’s
placement it not as critical.
5GND
Ground Contact for the driver stage. Keep traces physically short and
connect immediately to the ground plane for best performance. It is
important for stability that this pin has it’s own via to the groundplane, to
minimize any common inductance.
6RF IN
Amplifier RF input. This is a 50
Ω RF input port to the amplifier. It does
not contain internal DC blocking and therefore should be externally DC
blocked before connecting to any device which has DC present or
which contains a DC path to ground. A series UHF capacitor is recom-
mended for the DC blocking.
7NC
Not internally connected.
8
VPD
Power Down control. When this pin is “low” all circuits are off. A low is
typically less than 0.5V at room temperature. This pin affords a mea-
sure of power control, however this response is not linear across much
of the range. It is recommended that the pin be used in closed loop
power control systems if it is to be used across a range of voltages and
temperatures for power control.
9NC
Not internally connected.
10
NC
Not internally connected.
11
NC
Not internally connected.
12
RF OUT
Amplifier RF output. This is an unmatched collector output of the final
amplifier transistor. It is internally connected to pins 12, 13, and 14 to
provide low series inductance and flexibility in output matching. Bias for
the final power amplifier output transistor must also be provided
through two of these three pins. Typically, these pins are externally con-
nected very close to the package and used as the RF output with a
matching network that presents the optimum load impedance to the PA
for maximum power and efficiency, as well as providing DC blocking at
the output. An additional network of a bias inductor (or
λ/4 line) pro-
vides DC bias and helps to protect the output from high voltage swings
due to severe load mismatches.
13
RF OUT
Amplifier RF output, same as pin 12
14
RF OUT
Amplifier RF output, same as pin 12. Do not feed the supply to this pin
alone. If this pin is used as the supply pin it must be connected in paral-
lel with pin 12 and/or 13.
15
NC
Not internally connected.
16
NC
Not internally connected.
Pkg
Base
GND
This contact is the main ground contact for the entire device. Care
should be taken to ensure that this contact is well soldered in order to
prevent performance from being degraded from that indicated in the
specifications.
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