SC18IS602B

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Product data sheet

Rev. 5 — 3 August 2010

11 of 25

NXP Semiconductors

SC18IS602B

pulled LOW by an external device, the weak pull-up turns off, and only the very weak

pull-up remains on. In order to pull the pin LOW under these conditions, the external

device has to sink enough current to overpower the weak pull-up and pull the pin below its

input threshold voltage.

The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up

LOW-to-HIGH transitions on a quasi-bidirectional pin when the port latch changes from a

logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks

quickly pulling the pin HIGH.

The quasi-bidirectional pin configuration is shown in Figure 15.

Although the SC18IS602B is a 3 V device, most of the pins are 5 V tolerant. If 5 V is

applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from

configured in quasi-bidirectional mode is discouraged.

A quasi-bidirectional pin has a Schmitt-triggered input that also has a glitch suppression

circuit.

7.1.11.2

Open-drain output configuration

The open-drain output configuration turns off all pull-ups and only drives the pull-down

transistor of the pin when the port latch contains a logic 0. To be used as a logic output, a

pin configured in this manner must have an external pull-up, typically a resistor tied to

The open-drain pin configuration is shown in Figure 16.

An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit.

Fig 15. Quasi-bidirectional output configuration

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2 SYSTEM

CLOCK

CYCLES

weak

strong

very

weak

PP

P

pin latch data

GPIO pin

glitch rejection

input data