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SC18IS602B Datasheet(PDF) 7 Page - NXP Semiconductors |
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SC18IS602B Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 25 page SC18IS602B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 3 August 2010 7 of 25 NXP Semiconductors SC18IS602B I2C-bus to SPI bridge 7.1.5 Configure SPI Interface - Function ID F0h The SPI hardware operating mode, data direction, and frequency can be changed by sending a ‘Configure SPI Interface’ command to the I2C-bus. After the SC18IS602B address is transmitted on the bus, the Configure SPI Interface Function ID (F0h) is sent followed by a byte which will define the SPI communications. The Clock Phase bit (CPHA) allows the user to set the edges for sampling and changing data. The Clock Polarity bit (CPOL) allows the user to set the clock polarity. Figure 19 and Figure 20 show the different settings of Clock Phase bit CPHA. Fig 9. Configure SPI Interface Table 4. Configure SPI Interface (F0h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol X X ORDER X MODE1 MODE0 F1 F0 Reset X X 0 X 00 00 Table 5. Configure SPI Interface (F0h) bit description Bit Symbol Description 7:6 - reserved 5 ORDER When logic 0, the MSB of the data word is transmitted first. If logic 1, the LSB of the data word is transmitted first. 4 - reserved 3:2 MODE1:MODE0 Mode selection 00 - SPICLK LOW when idle; data clocked in on leading edge (CPOL = 0, CPHA = 0) 01 - SPICLK LOW when idle; data clocked in on trailing edge (CPOL = 0, CPHA = 1) 10 - SPICLK HIGH when idle; data clocked in on trailing edge (CPOL = 1, CPHA = 0) 11 - SPICLK HIGH when idle; data clocked in on leading edge (CPOL = 1, CPHA = 1) 1:0 F1:F0 SPI clock rate 00 - 1843 kHz 01 - 461 kHz 10 - 115 kHz 11 - 58 kHz A S 002aac450 P W SLAVE ADDRESS F0h A A DATA |
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