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HEF4894B Datasheet(PDF) 8 Page - NXP Semiconductors |
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HEF4894B Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 19 page HEF4894B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 7 — 13 August 2010 8 of 19 NXP Semiconductors HEF4894B 12-stage shift-and-store register LED driver [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). [2] ten is the same as tPZL and tdis is the same as tPLZ. [3] tt is the same as tTLH and tTHL. ten OE to QPn; see Figure 8 5V [2] -100 200 ns 10 V - 55 110 ns 15 V - 50 100 ns tdis OE to QPn; see Figure 8 5V [2] - 80 160 ns 10 V - 40 80 ns 15 V - 30 60 ns tt transition time QS1, QS2; see Figure 6 5V [1][3] 35 ns + (1.00 ns/pF)CL - 85 170 ns 10 V 19 ns + (0.42 ns/pF)CL -40 80 ns 15 V 16 ns + (0.28 ns/pF)CL -30 60 ns tW pulse width CP; LOW and HIGH; see Figure 6 5V 60 30 - ns 10 V 30 15 - ns 15 V 24 12 - ns STR; HIGH; see Figure 7 5V 80 40 - ns 10 V 60 30 - ns 15 V 24 12 - ns tsu set-up time D to CP; see Figure 9 5V 60 30 - ns 10 V 20 10 - ns 15 V 15 5 - ns th hold time D to CP; see Figure 9 5V +5 −15 - ns 10 V 20 5 - ns 15 V 20 5 - ns fclk(max) maximum clock frequency CP; see Figure 6 5V 5 10 - MHz 10 V 11 22 - MHz 15 V 14 28 - MHz Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 °C unless otherwise specified. For test circuit see Figure 10. Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit Table 8. Dynamic power dissipation PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter VDD Typical formula Where PD dynamic power dissipation 5V PD = 1200 × fi + Σ(fo × CL) × VDD2 μWfi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; Σ(f o × CL) = sum of the outputs; VDD = supply voltage in V. 10 V PD = 5550 × fi + Σ(fo × CL) × VDD2 μW 15 V PD = 15000 × fi + Σ(fo × CL) × VDD2 μW |
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