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P3P25814AG-08SR Datasheet(PDF) 3 Page - ON Semiconductor |
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P3P25814AG-08SR Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 9 page PCS3P25811 and PCS3P25812 and PCS3P25814 Rev. 1 | Page 3 of 9 | www.onsemi.com Input/Output Frequency Range Selection Table FSEL (pin 6) Part Number Modulation Rate PCS3P25811 (1x) PCS3P25812 (2x) PCS3P25814 (4x) Input (MHz) Output (MHz) Input (MHz) Output (MHz) Input (MHz) Output (MHz) 0 4-8 4-8 4-8 8-16 4-8 16-32 Input Frequency / 128 1 8-16 8-16 8-16 16-32 8-16 32-64 Input Frequency / 256 M 16-32 16-32 16-32 32-64 16-32 64-128 Input Frequency / 512 Output Frequency Deviation Selection Table CLKIN (MHz) FSEL S1=0 S0=0 S1=0 S0=M S1=0 S0=1 S1=M S0=0 S1=1 S0=1 S1=1 S0=0 S1=M S0=1 S1=1 S0=M S1=M S0=M Center Center Center Center Down Down Down Down No Spread 4-5 0 ±1.4 ±1.2 ±0.6 ±0.5 -3 -2.2 -1.9 -0.7 0 5-6 0 ±1.3 ±1.1 ±0.5 ±0.4 -2.7 -1.9 -1.7 -0.6 0 6-7 0 ±1.2 ±0.9 ±0.5 ±0.4 -2.5 -1.8 -1.5 -0.6 0 7-8 0 ±1.1 ±0.9 ±0.4 ±0.3 -2.3 -1.7 -1.4 -0.5 0 8-10 1 ±1.4 ±1.2 ±0.6 ±0.5 -3 -2.2 -1.9 -0.7 0 10-12 1 ±1.3 ±1.1 ±0.5 ±0.4 -2.7 -1.9 -1.7 -0.6 0 12-14 1 ±1.2 ±0.9 ±0.5 ±0.4 -2.5 -1.8 -1.5 -0.6 0 14-16 1 ±1.1 ±0.9 ±0.4 ±0.3 -2.3 -1.7 -1.4 -0.5 0 16-20 M ±1.4 ±1.2 ±0.6 ±0.5 -3 -2.2 -1.9 -0.7 0 20-24 M ±1.3 ±1.1 ±0.5 ±0.4 -2.7 -1.9 -1.7 -0.6 0 24-28 M ±1.2 ±0.9 ±0.5 ±0.4 -2.5 -1.8 -1.5 -0.6 0 28-32 M ±1.1 ±0.9 ±0.4 ±0.3 -2.3 -1.7 -1.4 -0.5 0 Note: Frequency Deviation given in the table is for the Input Frequency Range covering PCS3P25811/12 /14. 3 Level Digital Logic S0, S1, and FSEL digital inputs are designed to sense 3 different logic levels designated as High “1”, Low “0” and Middle “M”. With this 3-Level digital input logic 9 different logic states can be detected. S0, S1 and FSEL pins include an on chip 100K (50K/50K) resistor divider. No external application resistors are needed to implement the 3-Level logic levels as shown below: Logic Control Pins 1 FSEL, S0, S1 to VDD M FSEL, S0, S1 UNCONNECTED 0 FSEL, S0, S1 to VSS VSS VDD |
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