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XIO2213A Datasheet(PDF) 5 Page - Texas Instruments |
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XIO2213A Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 186 page  XIO2213A PCI Express to 1394b OHCI with 3-Port PHY www.ti.com SCPS183A – OCTOBER 2007 – REVISED MARCH 2008 7.17 Capability ID and Next Item Pointer Registers ....................................................................... 115 7.18 Power Management Capabilities Register ............................................................................ 116 7.19 Power Management Control and Status Register .................................................................... 116 7.20 Power Management Extension Registers ............................................................................. 117 7.21 PCI Miscellaneous Configuration Register ............................................................................ 118 7.22 Link Enhancement Control Register ................................................................................... 119 7.23 Subsystem Access Register ............................................................................................. 121 8 1394 OHCI Memory-Mapped Register Space ........................................................................ 122 8.1 OHCI Version Register ................................................................................................... 124 8.2 GUID ROM Register ..................................................................................................... 125 8.3 Asynchronous Transmit Retries Register .............................................................................. 126 8.4 CSR Data Register ...................................................................................................... 126 8.5 CSR Compare Register .................................................................................................. 127 8.6 CSR Control Register .................................................................................................... 127 8.7 Configuration ROM Header Register ................................................................................... 127 8.8 Bus Identification Register ............................................................................................... 128 8.9 Bus Options Register ..................................................................................................... 128 8.10 GUID High Register ...................................................................................................... 129 8.11 GUID Low Register ....................................................................................................... 130 8.12 Configuration ROM Mapping Register ................................................................................. 130 8.13 Posted Write Address Low Register ................................................................................... 130 8.14 Posted Write Address High Register ................................................................................... 131 8.15 Vendor ID Register ....................................................................................................... 131 8.16 Host Controller Control Register ........................................................................................ 131 8.17 Self-ID Buffer Pointer Register .......................................................................................... 133 8.18 Self-ID Count Register ................................................................................................... 133 8.19 Isochronous Receive Channel Mask High Register .................................................................. 134 8.20 Isochronous Receive Channel Mask Low Register .................................................................. 135 8.21 Interrupt Event Register .................................................................................................. 135 8.22 Interrupt Mask Register .................................................................................................. 137 8.23 Isochronous Transmit Interrupt Event Register ....................................................................... 139 8.24 Isochronous Transmit Interrupt Mask Register ....................................................................... 139 8.25 Isochronous Receive Interrupt Event Register ........................................................................ 140 8.26 Isochronous Receive Interrupt Mask Register ........................................................................ 140 8.27 Initial Bandwidth Available Register .................................................................................... 141 8.28 Initial Channels Available High Register ............................................................................... 141 8.29 Initial Channels Available Low Register ............................................................................... 142 8.30 Fairness Control Register ................................................................................................ 143 8.31 Link Control Register ..................................................................................................... 144 8.32 Node Identification Register ............................................................................................. 145 8.33 PHY Layer Control Register ............................................................................................. 146 8.34 Isochronous Cycle Timer Register ..................................................................................... 147 8.35 Asynchronous Request Filter High Register ......................................................................... 148 8.36 Asynchronous Request Filter Low Register ........................................................................... 150 8.37 Physical Request Filter High Register ................................................................................. 151 8.38 Physical Request Filter Low Register .................................................................................. 153 8.39 Physical Upper Bound Register (Optional Register) ................................................................. 153 8.40 Asynchronous Context Control Register ............................................................................... 154 8.41 Asynchronous Context Command Pointer Register .................................................................. 155 8.42 Isochronous Transmit Context Control Register ...................................................................... 156 8.43 Isochronous Transmit Context Command Pointer Register ......................................................... 157 8.44 Isochronous Receive Context Control Register ....................................................................... 157 8.45 Isochronous Receive Context Command Pointer Register ......................................................... 158 Contents 5 |
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