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CS1500-FSZ Datasheet(PDF) 11 Page - Cirrus Logic |
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CS1500-FSZ Datasheet(HTML) 11 Page - Cirrus Logic |
11 / 22 page CS1500 DS849A7 11 Jul ?$shortyear> CONFIDENTIAL greater than the peak of the line voltage (Vrect(pk)). The maximum response time of open/short loop protection for RFB is about 150 μs in the CS1500. If the PFC input sense resistor RAC fails (open or short to GND), the current reference signal supplied to the IC on pin IAC falls to zero. This failure is equivalent to a brownout condition and will be handled by the brownout protection mechanism described in Section 3.8. 3.12 Overcurrent Limiting Boost inductor saturation is a fatal condition for a PFC converter. To prevent inductor current saturation conditions, the IC utilizes a proprietary digital algorithm that keeps the boost inductor current away from its saturation current. The boost inductor should be designed for full load, minimal line voltage, maximum switching frequency, and with enough margin to prevent saturation in normal operation mode. 3.13 Standby (STBY) Function The standby (STBY) pin provides a means by which an external signal can cause the CS1500 to enter into a non- operating, low-power state. The STBY input is intended to be driven by an open-collector/open-drain device. Internal to the pin, there is a pull-up resistor connected to the VDD pin as shown in Figure 20. Since the pull-up resistor has a high impedance, the user may need to provide a filter capacitor (up to 1000 pF) on this pin. Figure 20. STBY Pin Connection When the STBY pin is not used, it is recommended that the pin be tied to VDD (pulled high). <1 nF 600 k Ω See Text VDD STBY GND CS1500 |
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