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SN65LVDT2DG4 Datasheet(PDF) 6 Page - Texas Instruments |
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SN65LVDT2DG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 22 page RECEIVER ELECTRICAL CHARACTERISTICS RECEIVER SWITCHING CHARACTERISTICS SN65LVDS1 SN65LVDS2 SN65LVDT2 SLLS373K – JULY 1999 – REVISED NOVEMBER 2008.................................................................................................................................................... www.ti.com over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX UNIT VITH+ Positive-going differential input voltage threshold 100 See Figure 3 mV VITH– Negative-going differential input voltage threshold –100 IOH = –8 mA, VCC = 2.4 V 1.9 VOH High-level output voltage V IOH = –8 mA, VCC = 3 V 2.4 VOL Low-level output voltage IOL = 8 mA 0.25 0.4 V ICC Supply current No load, Steady state 4 7 mA VI = 0 V, other input = 1.2 V –20 –2 LVDS2 VI = 2.2 V, other input = 1.2 V, –3 –1.2 VCC = 3.0 V II Input current (A or B inputs) µA VI = 0 V, other input open –40 -4 LVDT2 VI = 2.2 V, other input open, VCC = 3.0 V –6 –2.4 IID Differential input current (IIA – IIB) LVDS2 VIA = 2.4 V VIB = 2.3 V –2 2 µA LVDS2 VCC = 0 V, VIA = VIB = 2.4 V 20 II(OFF) Power-off input current (A or B inputs) µA LVDT2 VCC = 0 V, VIA = VIB = 2.4 V 40 RT Differential input resistance LVDT2 VIA = 2.4 V VIB = 2.2 V 90 111 132 Ω CI Input Capacitance VI = 0.4sin(4E6πt) + 0.5V 5.8 pF CO Output Capacitance VI = 0.4sin(4E6πt) + 0.5V 3.4 pF (1) The algebraic convention, in which the least positive (most negative) limit is designated as a minimum, is used in this data sheet. (2) All typical values are at 25°C and with a 2.7-V supply. over recommended operating conditions (unless otherwise noted) TYP( PARAMETER TEST CONDITIONS MIN MAX UNIT 1) Propagation delay time, low-to-high-level tPLH 1.4 2.6 3.6 ns output Propagation delay time, high-to-low-level tPHL 1.4 2.5 3.6 ns CL = 10 pF, See Figure 6 output tsk(p) Pulse skew (|tpHL – tpLH|) (2) 0.1 0.6 ns tr Output signal rise time 0.8 1.4 ns tf Output signal fall time 0.8 1.4 ns VCC = 3.0 V - 3.6 V 2.2 3 5.5 V/ns tr(slew) Output slew rate (rising) VCC = 2.4 V - 2.7 V 1.5 1.9 2.9 V/ns CL = 10 pF VCC = 3.0 V - 3.6 V 2.7 3.8 6 V/ns tf(slew) Output slew rate (falling) VCC = 2.4 V - 2.7 V 2.1 2.3 3.9 V/ns (1) All typical values are at 25°C and with a 2.7-V supply. (2) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. 6 Submit Documentation Feedback Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 |
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