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SN65LVDT2D Datasheet(PDF) 3 Page - Texas Instruments |
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SN65LVDT2D Datasheet(HTML) 3 Page - Texas Instruments |
3 / 22 page RECEIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS 7 V VCC 7 V R Output VCC 5 Ω A Input 300 k Ω 300 k Ω 7 V B Input 110- Ω LVDT Only ABSOLUTE MAXIMUM RATINGS DISSIPATION RATING TABLE SN65LVDS1 SN65LVDS2 SN65LVDT2 www.ti.com.................................................................................................................................................... SLLS373K – JULY 1999 – REVISED NOVEMBER 2008 over operating free-air temperature range (unless otherwise noted) (1) PARAMETER RATINGS Supply voltage range, VCC (2) –0.5 V to 4 V (A or B) –0.5 V to 4 V Input voltage range, VI (D) –0.5 V to VCC + 2 V Output voltage, VO (Y or Z) –0.5 V to 4 V Differential input voltage SN65LVDT2 only 1 V magnitude, |VID| Receiver output current, IO -12 mA to 12 mA Human-body model electrostatic discharge, HBM ESD(3) All pins 4000 V Bus pins (A, B, Y, Z) 9000 V Machine-model electrostatic discharge, MM ESD(4) 400 V Field-induced-charge device model electrostatic discharge, FCDM ESD(5) 1500 V Continuous total power dissipation, PD See Dissipation Rating Table Storage Temperature Range (non operating) –65°C to 150°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages are with respect to network ground terminal. (3) Test method based upon JEDEC Standard 22, Test Method A114-A. Bus pins stressed with respect to GND and VCC separately. (4) Test method based upon JEDEC Standard 22, Test Method A114-A. (5) Test method based upon EIA-JEDEC JESD22-C101C. TA ≤ 25°C DERATING FACTOR TA = 85°C PACKAGE POWER RATING ABOVE TA = 25°C (1) POWER RATING D 725 mW 5.8 mW/°C 402 mW DBV 385 mW 3.1 mW/°C 200 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-K) and with no air flow. Copyright © 1999–2008, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 |
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