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ADS62P48IRGCR Datasheet(PDF) 10 Page - Texas Instruments |
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ADS62P48IRGCR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 77 page TIMING REQUIREMENTS – LVDS AND CMOS MODES (1) ADS62P49 / ADS62P29 ADS62P48 / ADS62P28 SLAS635A – APRIL 2009 – REVISED JUNE 2009............................................................................................................................................................. www.ti.com Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock, 1.5 Vpp clock amplitude, CLOAD = 5pF (2) , R LOAD = 100Ω (3) , (unless otherwise noted). Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.7V to 1.9V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ta Aperture delay 0.7 1.2 1.7 ns Aperture delay matching Between two channels within the same device ±50 ps tj Aperture jitter 145 fs rms Time to valid data after coming out of STANDBY mode 1 3 µs Time to valid data after coming out of global powerdown 20 50 µs Wake-up time Time to valid data after stopping and restarting the input clock 10 Clock cycles Clock ADC latency(4) 22 cycles DDR LVDS MODE(5) tsu Data setup time Data valid(6) to zero-crossing of CLKOUTP 0.55 0.9 ns th Data hold time Zero-crossing of CLKOUTP to data becoming invalid(6) 0.55 0.95 ns tPDI Input clock falling edge cross-over to output clock rising edge tPDI = 0.69×Ts + tdelay cross-over Clock propagation delay 100 MSPS ≤ Sampling frequency ≤ 250 MSPS tdelay 4.2 5.7 7.2 ns Ts = 1/Sampling frequency Difference in tdelay between two devices operating at same tdelay skew ±500 ps temperature and DRVDD supply voltage Duty cycle of differential clock, (CLKOUTP-CLKOUTM) LVDS bit clock duty cycle 52% 100 MSPS ≤ Sampling frequency ≤ 250 MSPS Rise time measured from –100mV to +100mV tRISE, Data rise time, Fall time measured from +100mV to –100mV 0.14 ns tFALL Data fall time 1MSPS ≤ Sampling frequency ≤ 250 MSPS Rise time measured from –100mV to +100mV tCLKRISE, Output clock rise time, Fall time measured from +100mV to –100mV 0.14 ns tCLKFALL Output clock fall time 1 MSPS ≤ Sampling frequency ≤ 250 MSPS Output buffer enable to tOE Time to valid data after output buffer becomes active 100 ns data delay PARALLEL CMOS MODE(7) at Fs = 210 MSPS tSTART Input clock to data delay Input clock falling edge cross-over to start of data valid(8) 2.5 ns tDV Data valid time Time interval of valid data(8) 1.7 2.7 ns tPDI Input clock falling edge cross-over to output clock rising edge tPDI = 0.28 × Ts + tdelay cross-over Clock propagation delay 100 MSPS ≤ Sampling frequency ≤ 150 MSPS tdelay 5.5 7.0 8.5 ns Ts = 1/Sampling frequency Duty cycle of output clock, CLKOUT Output clock duty cycle 43% 100 MSPS ≤ Sampling frequency ≤ 150 MSPS Rise time measured from 20% to 80% of DRVDD tRISE, Data rise time, Fall time measured from 80% to 20% of DRVDD 1.2 ns tFALL Data fall time 1 ≤ Sampling frequency ≤ 210 MSPS Rise time measured from 20% to 80% of DRVDD tCLKRISE, Output clock rise time, Fall time measured from 80% to 20% of DRVDD 0.8 ns tCLKFALL Output clock fall time 1 ≤ Sampling frequency ≤ 150 MSPS (1) Timing parameters are ensured by design and characterization and not tested in production (2) CLOAD is the effective external single-ended load capacitance between each output pin and ground (3) RLOAD is the differential load resistance between the LVDS output pair. (4) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1. (5) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. (6) Data valid refers to LOGIC HIGH of +100.0mV and LOGIC LOW of –100.0mV. (7) For Fs> 150 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). (8) Data valid refers to LOGIC HIGH of 1.26V and LOGIC LOW of 0.54V. 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28 |
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