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ADS62P49 Datasheet(PDF) 6 Page - Texas Instruments |
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ADS62P49 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 77 page  ELECTRICAL CHARACTERISTICS – ADS62P49/48 and ADS62P29/28 ADS62P49 / ADS62P29 ADS62P48 / ADS62P28 SLAS635A – APRIL 2009 – REVISED JUNE 2009............................................................................................................................................................. www.ti.com Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V ADS62P49/ADS62P29 ADS62P48/ADS62P28 250 MSPS 210 MSPS PARAMETER UNIT MIN TYP MAX MIN TYP MAX ANALOG INPUT Differential input voltage range (0 dB gain) 2 2 Vpp Differential input resistance (at dc), See Figure 94 > 1 > 1 M Ω Differential input capacitance, See Figure 95 3.5 3.5 pF Analog input bandwidth (with 25 Ω source impedance) 700 700 MHz Analog Input common mode current (per channel) 3.6 3.6 µA/MSPS VCM Common mode output voltage 1.5 1.5 V VCM Output current capability ±4 ±4 mA DC ACCURACY Offset error –20 ±2 20 –20 ±2 20 mV Temperature coefficient of offset error 0.02 0.02 mV/ °C Variation of offset error with supply 0.5 0.5 mV/V There are two sources of gain error – internal reference inaccuracy and channel gain error. EGREF Gain error due to internal reference inaccuracy alone –1 ±0.2 1 –1 ±0.2 1 % FS EGCHAN Gain error of channel alone(1) –1 ±0.2 1 –1 ±0.2 1 % FS Temperature coefficient of EGCHAN 0.002 0.002 Δ% /°C Difference in gain errors between two channels –2 2 –2 2 Gain within the same device matching % FS Difference in gain errors between two channels (2) –4 4 –4 4 across two devices POWER SUPPLY IAVDD Analog supply current 305 350 280 320 mA Output buffer supply current, LVDS interface with 100 Ω IDRVDD 133 175 122 165 mA external termination Output buffer supply current, CMOS interface, Fin = 2MHz, IDRVDD – 91 mA No external load capacitance (3)(4) Analog power 1.01 1.15 0.92 1.05 W Digital power, LVDS interface 0.24 0.315 0.22 0.3 W Global power down 45 100 45 100 mW (1) This is specified by design and characterization; it is not tested in production. (2) For two channels within the same device, only the channel gain error matters, as the reference is common for both channels. (3) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency and the supply voltage (see Figure 86 and CMOS interface power dissipation in application section). (4) The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the maximum recommended load capacitance on each digital output line is 10 pF. 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28 |
Similar Part No. - ADS62P49_1 |
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Similar Description - ADS62P49_1 |
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