TPS783xx

SBVS133 – FEBRUARY 2010

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

AVAILABLE OPTIONS

(1)

TPS78315

TPS78318

TPS78319

TPS78320

TPS78322

TPS78323

TPS78325

TPS78326

Output

1.5

1.8

1.9

2.0

2.2

2.3

2.5

2.6

Voltage (V)

TPS78328

TPS78329

TPS78330

TPS78332

TPS78333

TPS78336

TPS78342

Output

2.8

2.9

3.0

3.2

3.3

3.6

4.2

Voltage (V)

(1)

Additional output voltage options are available on a quick-turn basis using innovative, factory EEPROM programming. Minimum-order

quantities may apply; contact your sales representative for details and availability

PRODUCT

TPS783xxyyyz

XX is the nominal output voltage

YYY is the package designator.

Z is the tape and reel quantity (R = 3000, T = 250).

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

PARAMETER

TPS783xx

UNIT

–0.3 to +6.0

V

Enable

V

V

Internally limited

Output short-circuit duration

Indefinite

See Dissipation Ratings Table

Human body model (HBM)

2

kV

ESD rating

Charged device model (CDM)

500

V

–40 to +105

°C

–55 to +150

°C

(1)

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

DISSIPATION RATINGS

DERATING FACTOR

BOARD

PACKAGE

DDC

90°C/W

200°C/W

5.0mW/°C

500mW

275mW

200mW

(1)

The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and

ground planes and 2-ounce copper traces on top and bottom of the board.

2

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