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ADS62C17 Datasheet(PDF) 9 Page - Texas Instruments |
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ADS62C17 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 67 page  TIMING CHARACTERISTICS — LVDS AND CMOS MODES (1) ADS62C17 www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009 Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, sine wave input clock, CLOAD = 5pF (2), R LOAD = 100 Ω (3), no internal termination, LOW SPEED mode disabled, unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.7V to 1.9V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ta Aperture delay 0.7 1.2 1.7 ns Aperture delay matching between two channels of the same device ±50 ps tj Aperture jitter 145 fs rms Time to valid data after coming out of STANDBY mode 1 3 µs Wake-up time Time to valid data after coming out of global powerdown 20 50 Time to valid data after stopping and restarting the input clock 10 Clock cycles ADC Latency(4) Default, after reset 22 DDR LVDS MODE(5) tsu Data setup time(6) Data valid(7) to zero-crossing of CLKOUTP 0.8 1.15 ns th Data hold time(7) Zero-crossing of CLKOUTP to data becoming invalid(7) 0.8 1.15 ns tPDI Clock propagation delay Input clock falling edge cross-over to output clock rising edge tPDI = 0.69×Ts + tdelay cross-over 100 MSPS ≤ Sampling frequency ≤ 200 MSPS tdelay 4.2 5.7 7.2 ns Ts = 1/Sampling frequency Difference in tdelay between two devices operating at same tdelay skew ±500 ps temperature & SVDD supply voltage. Duty cycle of differential clock, (CLKOUTP-CLKOUTM) LVDS bit clock duty cycle 52% 100 MSPS ≤ Sampling frequency ≤ 200 MSPS Rise time measured from –100 mV to +100 mV tRISE, tFALL Data rise time, Data fall time Fall time measured from +100 mV to –100 mV 0.14 ns 1MSPS ≤ Sampling frequency ≤ 200 MSPS Rise time measured from –100 mV to +100 mV Output clock rise time, tCLKRISE, Fall time measured from +100 mV to –100 mV 0.14 ns tCLKFALL Output clock fall time 1 MSPS ≤ Sampling frequency ≤ 200 MSPS tOE Output buffer enable to data delay Time to valid data after output buffer becomes active 100 ns PARALLEL CMOS MODE at Fs=200 MSPS(8) tSTART Input clock to data delay Input clock falling edge cross-over to start of data valid(7) 2.5 ns tDV Data valid time Time interval of valid data(7) 1.7 2.7 ns tPDI Clock propagation delay Input clock falling edge cross-over to output clock rising edge tPDI = 0.28×Ts + tdelay cross-over 100 MSPS ≤ Sampling frequency ≤ 150 MSPS tdelay 5.5 7.5 8.5 ns Ts = 1/Sampling frequency Duty cycle of output clock, CLKOUT Output clock duty cycle 43 100 MSPS ≤ Sampling frequency ≤ 150 MSPS Rise time measured from 20% to 80% of DRVDD tRISE, tFALL Data rise time, Data fall time Fall time measured from 80% to 20% of DRVDD 1.2 ns 1 ≤ Sampling frequency ≤ 200 MSPS Rise time measured from 20% to 80% of DRVDD Output clock rise time, tCLKRISE, Fall time measured from 80% to 20% of DRVDD 0.8 ns tCLKFALL Output clock fall time 1 ≤ Sampling frequency ≤ 150 MSPS Output buffer enable (OE) to data tOE Time to valid data after output buffer becomes active 100 ns delay (1) Timing parameters are ensured by design and characterization and not tested in production. (2) CLOAD is the effective external single-ended load capacitance between each output pin and ground (3) RLOAD is the differential load resistance between the LVDS output pair. (4) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1. (5) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. (6) Data valid refers to LOGIC HIGH of +100.0mV and LOGIC LOW of -100.0mV. (7) Data valid refers to LOGIC HIGH of 1.26V and LOGIC LOW of 0.54V. (8) For Fs> 150 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): ADS62C17 |
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