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TS3DV421 Datasheet(PDF) 4 Page - Texas Instruments |
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TS3DV421 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 19 page TS3DV421 SCDS264D – JANUARY 2008 – REVISED JANUARY 2010 www.ti.com TERMINAL FUNCTIONS TERMINAL NO. TYPE DESCRIPTION NAME QFN (RUA) TVSOP (DGV) ATMDS0– 33 40 I/O Port A, channel 0, TMDS negative signal ATMDS0+ 34 41 I/O Port A, channel 0, TMDS positive signal ATMDS1– 35 43 I/O Port A, channel 1, TMDS negative signal ATMDS1+ 36 44 I/O Port A, channel 1, TMDS positive signal ATMDS2– 37 45 I/O Port A, channel 2, TMDS negative signal ATMDS2+ 38 46 I/O Port A, channel 2, TMDS positive signal ATMDSCLK– 31 38 I/O Port A TMDS negative clock ATMDSCLK+ 32 39 I/O Port A TMDS positive clock BTMDS0– 24 29 I/O Port B, channel 0, TMDS negative signal BTMDS0+ 25 30 I/O Port B, channel 0, TMDS positive signal BTMDS1– 26 32 I/O Port B, channel 1, TMDS negative signal BTMDS1+ 27 33 I/O Port B, channel 1, TMDS positive signal BTMDS2– 28 34 I/O Port B, channel 2, TMDS negative signal BTMDS2+ 29 35 I/O Port B, channel 2, TMDS positive signal BTMDSCLK– 22 27 I/O Port B TMDS negative clock BTMDSCLK+ 23 28 I/O Port B TMDS positive clock SEL 9 13 I Select pin to choose between port A or port B. Referenced to VSS TMDS0– 12 16 I/O TMDS channel 0 negative signal TMDS0+ 11 15 I/O TMDS channel 0 positive signal TMDS1– 7 10 I/O TMDS channel 1 negative signal TMDS1+ 6 9 I/O TMDS channel 1 positive signal TMDS2– 4 7 I/O TMDS channel 2 negative signal TMDS2+ 3 6 I/O TMDS channel 2 positive signal TMDSCLK– 15 19 I/O TMDS negative clock TMDSCLK+ 14 18 I/O TMDS positive clock 2, 8, 16, 2, 4, 12, VDD 18, 20, 30, 21, 23, 25, Power Positive power supply voltage 40, 42 36, 48 1, 3, 5, 1, 5, 10, 8, 14, 17, VSS 13, 17, 19, 20, 22, 24, Power Negative power supply voltage 21, 39, 41 26, 31, 37, 42, 47 4 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TS3DV421 |
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