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LM3S8962-EQN50-A2 Datasheet(PDF) 3 Page - Texas Instruments |
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LM3S8962-EQN50-A2 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 684 page Table of Contents Revision History ............................................................................................................................. 22 About This Document .................................................................................................................... 27 Audience .............................................................................................................................................. 27 About This Manual ................................................................................................................................ 27 Related Documents ............................................................................................................................... 27 Documentation Conventions .................................................................................................................. 28 1 Architectural Overview .......................................................................................... 30 1.1 Product Features .......................................................................................................... 30 1.2 Target Applications ........................................................................................................ 39 1.3 High-Level Block Diagram ............................................................................................. 40 1.4 Functional Overview ...................................................................................................... 42 1.4.1 ARM Cortex™-M3 ......................................................................................................... 42 1.4.2 Motor Control Peripherals .............................................................................................. 43 1.4.3 Analog Peripherals ........................................................................................................ 43 1.4.4 Serial Communications Peripherals ................................................................................ 44 1.4.5 System Peripherals ....................................................................................................... 46 1.4.6 Memory Peripherals ...................................................................................................... 47 1.4.7 Additional Features ....................................................................................................... 47 1.4.8 Hardware Details .......................................................................................................... 48 2 ARM Cortex-M3 Processor Core ........................................................................... 49 2.1 Block Diagram .............................................................................................................. 50 2.2 Functional Description ................................................................................................... 50 2.2.1 Serial Wire and JTAG Debug ......................................................................................... 50 2.2.2 Embedded Trace Macrocell (ETM) ................................................................................. 51 2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 51 2.2.4 ROM Table ................................................................................................................... 51 2.2.5 Memory Protection Unit (MPU) ....................................................................................... 51 2.2.6 Nested Vectored Interrupt Controller (NVIC) .................................................................... 51 3 Memory Map ........................................................................................................... 55 4 Interrupts ................................................................................................................. 58 5 JTAG Interface ........................................................................................................ 61 5.1 Block Diagram .............................................................................................................. 62 5.2 Functional Description ................................................................................................... 62 5.2.1 JTAG Interface Pins ...................................................................................................... 62 5.2.2 JTAG TAP Controller ..................................................................................................... 64 5.2.3 Shift Registers .............................................................................................................. 65 5.2.4 Operational Considerations ............................................................................................ 65 5.3 Initialization and Configuration ....................................................................................... 68 5.4 Register Descriptions .................................................................................................... 68 5.4.1 Instruction Register (IR) ................................................................................................. 68 5.4.2 Data Registers .............................................................................................................. 70 6 System Control ....................................................................................................... 73 6.1 Functional Description ................................................................................................... 73 6.1.1 Device Identification ...................................................................................................... 73 3 June 22, 2010 Texas Instruments-Production Data Stellaris® LM3S8962 Microcontroller |
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