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LM3S8933-EGZ20-A2 Datasheet(PDF) 10 Page - Texas Instruments |
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LM3S8933-EGZ20-A2 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 618 page Figure 15-1. I2C Block Diagram ............................................................................................. 398 Figure 15-2. I2C Bus Configuration ........................................................................................ 398 Figure 15-3. START and STOP Conditions ............................................................................. 399 Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 399 Figure 15-5. R/S Bit in First Byte ............................................................................................ 399 Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 400 Figure 15-7. Master Single SEND .......................................................................................... 403 Figure 15-8. Master Single RECEIVE ..................................................................................... 404 Figure 15-9. Master Burst SEND ........................................................................................... 405 Figure 15-10. Master Burst RECEIVE ...................................................................................... 406 Figure 15-11. Master Burst RECEIVE after Burst SEND ............................................................ 407 Figure 15-12. Master Burst SEND after Burst RECEIVE ............................................................ 408 Figure 15-13. Slave Command Sequence ................................................................................ 409 Figure 16-1. CAN Controller Block Diagram ............................................................................ 434 Figure 16-2. CAN Data/Remote Frame .................................................................................. 435 Figure 16-3. Message Objects in a FIFO Buffer ...................................................................... 443 Figure 16-4. CAN Bit Time .................................................................................................... 447 Figure 17-1. Ethernet Controller ............................................................................................. 482 Figure 17-2. Ethernet Controller Block Diagram ...................................................................... 482 Figure 17-3. Ethernet Frame ................................................................................................. 483 Figure 17-4. Interface to an Ethernet Jack .............................................................................. 489 Figure 18-1. Analog Comparator Module Block Diagram ......................................................... 530 Figure 18-2. Structure of Comparator Unit .............................................................................. 531 Figure 18-3. Comparator Internal Reference Structure ............................................................ 531 Figure 19-1. 100-Pin LQFP Package Pin Diagram .................................................................. 541 Figure 19-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 542 Figure 22-1. Load Conditions ................................................................................................ 575 Figure 22-2. JTAG Test Clock Input Timing ............................................................................. 577 Figure 22-3. JTAG Test Access Port (TAP) Timing .................................................................. 578 Figure 22-4. JTAG TRST Timing ............................................................................................ 578 Figure 22-5. External Reset Timing (RST) .............................................................................. 579 Figure 22-6. Power-On Reset Timing ..................................................................................... 579 Figure 22-7. Brown-Out Reset Timing .................................................................................... 579 Figure 22-8. Software Reset Timing ....................................................................................... 579 Figure 22-9. Watchdog Reset Timing ..................................................................................... 580 Figure 22-10. Hibernation Module Timing ................................................................................. 581 Figure 22-11. ADC Input Equivalency Diagram ......................................................................... 582 Figure 22-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .................................................................................................... 583 Figure 22-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 583 Figure 22-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 584 Figure 22-15. I2C Timing ......................................................................................................... 585 Figure 22-16. External XTLP Oscillator Characteristics ............................................................. 587 Figure D-1. 100-Pin LQFP Package ...................................................................................... 614 Figure D-2. 108-Ball BGA Package ...................................................................................... 616 June 22, 2010 10 Texas Instruments-Production Data Table of Contents |
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