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LM3S9B81-IQN80-C1T Datasheet(PDF) 3 Page - Texas Instruments |
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LM3S9B81-IQN80-C1T Datasheet(HTML) 3 Page - Texas Instruments |
3 / 1155 page Table of Contents Revision History ............................................................................................................................. 35 About This Document .................................................................................................................... 40 Audience .............................................................................................................................................. 40 About This Manual ................................................................................................................................ 40 Related Documents ............................................................................................................................... 40 Documentation Conventions .................................................................................................................. 41 1 Architectural Overview .......................................................................................... 43 1.1 Functional Overview ...................................................................................................... 45 1.1.1 ARM Cortex™-M3 ......................................................................................................... 45 1.1.2 On-Chip Memory ........................................................................................................... 47 1.1.3 External Peripheral Interface ......................................................................................... 48 1.1.4 Serial Communications Peripherals ................................................................................ 49 1.1.5 System Integration ........................................................................................................ 55 1.1.6 Analog .......................................................................................................................... 60 1.1.7 JTAG and ARM Serial Wire Debug ................................................................................ 62 1.1.8 Packaging and Temperature .......................................................................................... 62 1.2 Target Applications ........................................................................................................ 62 1.3 High-Level Block Diagram ............................................................................................. 63 1.4 Additional Features ....................................................................................................... 65 1.4.1 Memory Map ................................................................................................................ 65 1.4.2 Hardware Details .......................................................................................................... 65 2 ARM Cortex-M3 Processor Core ........................................................................... 66 2.1 Block Diagram .............................................................................................................. 67 2.2 Functional Description ................................................................................................... 67 2.2.1 Programming Model ...................................................................................................... 67 2.2.2 Serial Wire and JTAG Debug ......................................................................................... 74 2.2.3 Embedded Trace Macrocell (ETM) ................................................................................. 74 2.2.4 Trace Port Interface Unit (TPIU) ..................................................................................... 74 2.2.5 ROM Table ................................................................................................................... 75 2.2.6 Memory Protection Unit (MPU) ....................................................................................... 75 2.2.7 Nested Vectored Interrupt Controller (NVIC) .................................................................... 75 2.2.8 System Timer (SysTick) ................................................................................................. 76 3 Memory Map ........................................................................................................... 79 4 Interrupts ................................................................................................................. 82 5 JTAG Interface ........................................................................................................ 85 5.1 Block Diagram .............................................................................................................. 86 5.2 Signal Description ......................................................................................................... 86 5.3 Functional Description ................................................................................................... 87 5.3.1 JTAG Interface Pins ...................................................................................................... 87 5.3.2 JTAG TAP Controller ..................................................................................................... 89 5.3.3 Shift Registers .............................................................................................................. 89 5.3.4 Operational Considerations ............................................................................................ 90 5.4 Initialization and Configuration ....................................................................................... 92 5.5 Register Descriptions .................................................................................................... 93 3 June 29, 2010 Texas Instruments-Advance Information Stellaris® LM3S9B81 Microcontroller |
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