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NCV7513AFTG Datasheet(PDF) 7 Page - ON Semiconductor

Part # NCV7513AFTG
Description  FLEXMOS Hex Low-Side MOSFET Pre-Driver
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCV7513AFTG Datasheet(HTML) 7 Page - ON Semiconductor

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NCV7513A
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ELECTRICAL CHARACTERISTICS (continued) (4.75 VvVCCXv5.25 V, VDD = VCCX, −40°CvTJv125°C, unless otherwise
specified.) (Note 6)
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
Fault Detection – GATX OFF
DRNX Diagnostic Current
ISG
Short to GND Detection,
VDRNX = 0.30 VCC1
−27
−20
−10
mA
IOL
Open Load Detection,
VDRNX = 0.75 VCC1
30
60
80
mA
DRNX Fault Threshold Voltage
VSG
Short to GND Detection
27
30
33
%VCC1
VOL
Open Load Detection
72
75
78
%VCC1
DRNX Off State Bias Voltage
VCTR
50
%VCC1
Gate Driver Outputs
GATX Output Resistance
Output High or Low
1.0
1.80
2.5
kW
GATX High Output Current
VGATX = 0 V
−5.25
−1.9
mA
GATX Low Output Current
VGATX = VCC2
1.9
5.25
mA
Turn−On Propagation Delay
tP(ON)
INX to GATX (Figure 4)
1.0
ms
CSB to GATX (Figure 5)
Turn−Off Propagation Delay
tP(OFF)
INX to GATX (Figure 4)
1.0
ms
CSB to GATX (Figure 5)
Output Rise Time
tR
20% to 80% of VCC2,
CLOAD = 400 pF
(Figure 4, Note 5)
1.40
ms
Output Fall Time
tF
80% to 20% of VCC2,
CLOAD = 400 pF
(Figure 4, Note 5)
1.40
ms
Fault Timers
Channel Fault Blanking Timer
tBL(ON)
VDRNX = 5.0 V; INX rising to
FLTB falling (Figure 6)
30
45
60
ms
tBL(OFF)
VDRNX = 0 V; INX falling to
FLTB falling (Figure 6)
90
120
150
ms
Channel Fault Filter Timer
tFF
Figure 7
7.0
12
17
ms
Global Fault Refresh Timer
(Auto−retry Mode)
tFR
Register 2: Bit R2 = 0 or R5 = 0
7.5
10
12.5
ms
Register 2: Bit R2 = 1 or R5 = 1
30
40
50
ms
Timer Clock
ENA1 = 1
500
kHz
Serial Peripheral Interface (Figure 9) Vccx = 5.0 V, VDD = 3.3 V, FSCLK = 4.0 MHz, CLOAD = 200 pF
SO Supply Voltage
VDD
3.3 V Interface
3.0
3.3
3.6
V
5.0 V Interface
4.5
5.0
5.5
V
SCLK Clock Period
250
ns
Maximum Input Capacitance
Sl, SCLK (Note 7)
12
pF
SCLK High Time
SCLK = 2.0 V to 2.0 V
125
ns
SCLK Low Time
SCLK = 0.8 V to 0.8 V
125
ns
Sl Setup Time
Sl = 0.8 V/2.0 V to
SCLK = 2.0 V (Note 7)
25
ns
Sl Hold Time
SCLK = 2.0 V to
Sl = 0.8 V/2.0 V (Note 7)
25
ns
6. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100%
parametrically tested in production.
7. Guaranteed by design.


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