DEVICE INFORMATION

Digital Inputs

Limiter

I

= I

INmax

LIM

5 V

I

LIM

I

IN

IPx

R

LIM

I

Mirror

n = 72

LIM

I

REF

V-REF

R

=

LIM

90

I

LIM

90

2.5 mA

= 36 k

=

Debounce Filter

SN65HVS882

Figure 12. Digital Input Stage

further reduce the power consumption. For example, for a current limit of 2.5 mA simply calculate:

The HVS882 applies a simple analog/digital filtering technique to remove unintended signal transitions due to

contact bounce or other mechanical effects. Any new input (either low or high) must be present for the duration

of the selected debounce time to be latched into the shift register as a valid state.

The logic signal levels at the control inputs, DB0 and DB1 of the internal Debounce-Select logic determine the

different debounce times listed in the following truth table.

Table 1. Debounce Times

DB1

DB0

FUNCTION

Open

Open

3 ms delay

Open

GND

1 ms delay

0 ms delay

GND

Open

(filter bypassed)

GND

GND

Reserved

10

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