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NCP5111PG Datasheet(PDF) 5 Page - ON Semiconductor |
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NCP5111PG Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 14 page NCP5111 http://onsemi.com 5 IN DRV_HI DRV_LO Figure 4. Input/Output Timing Diagram Note: DRV_HI output is in phase with the input. Figure 5. Timing Definitions 50% 90% 50% ton toff 10% DRV_HI IN 10% toff 90% DRV_LO tr 90% Dead Time 10% tf ton = toff + DT 90% tf 10% Dead Time ton tr Figure 6. Matching Propagation Delay 50% 90% 50% toff_HI 10% DRV_HI IN 10% toff_LO 90% DRV_LO Dead Time 1 Matching Delay 1 = toff_HI - toff_LO Dead Time 2 Matching Delay 2 = (toff_LO + DT1) - (toff_HI + DT2) |
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