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PCF8574NE4 Datasheet(PDF) 5 Page - Texas Instruments |
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PCF8574NE4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 26 page A A S 0 1 0 0 A1 A2 A0 0 Start Condition ACK From Slave ACK From Slave Data Data Slave Address R/W P7 P6 1 P0 P7 P0 A Integral Multiples of Two Bytes P5 tpv IOHT tir SCL SDA Write to Port Data Output Voltage P5 Output Voltage P5 Pullup Output Current INT ACK From Slave Data A0 and B0 Valid 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 IOH A A S 0 1 0 0 A1 A2 A0 1 ACK From Slave ACK From Master R/W P7 P6 P0 P7 ACK From Master tsu tir SCL SDA Read From Port Data Into Port INT P5 P4 P3 P2 P1 A P0 tir tiv P7 to P0 A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). The transfer of data can be stopped at any moment by a stop condition. When this occurs, data present at the latest ACK phase is valid (output mode). Input data is lost. P6 P5 P4 P3 P2 P1 th P7 P6 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 P7 to P0 PCF8574 www.ti.com ............................................................................................................................................................... SCPS068G – JULY 2001 – REVISED MAY 2008 Figure 1 and Figure 2 show the address and timing diagrams for the write and read modes, respectively. Figure 1. Write Mode (Output) Figure 2. Read Mode (Input) Copyright © 2001–2008, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): PCF8574 |
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