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PGA870IRHDR Datasheet(PDF) 5 Page - Texas Instruments |
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PGA870IRHDR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 26 page LATCHMODE V S+ IN+ V MID2 IN- V S+ GAINSTROBE GND V S+ OUT+ GND OUT- V S+ GND 1 2 3 4 5 6 7 21 20 19 18 17 16 15 PowerPADä PGA870 www.ti.com SBOS436 – DECEMBER 2009 PIN CONFIGURATION QFN-28 RHD PACKAGE (TOP VIEW) PIN ASSIGNMENTS PIN NUMBER PIN NAME DESCRIPTION Controls latched and unlatched acquisition of the gain control word (B0 to B5). See the application section Gain 1 LATCH MODE Control Modes for a detailed description. 2, 6, 11, 16, 20, 25 VS+ +5V power supply 3 IN+ Noninverting input Buffer output for the internal midsupply reference. This point is the output of an active buffer which is not intended 4 VMID2 to drive an external load. It should be bypassed by a 0.1- μF capacitor. 5 IN– Inverting input 7 GAIN STROBE Gain latch clock pin 8 B5 (MSB) Gain control MSB 9 B4 Gain control bit 4 10 B3 Gain control bit 3 12 B2 Gain control bit 2 13 B1 Gain control bit 1 14 B0 (LSB) Gain control bit 0 17 OUT– Inverting output 15, 18, 21, 22, 23, GND Ground 24, 26 19 OUT+ Noninverting output 27 PD Active low power-down for device analog circuitry. Gain control CMOS circuitry is still active when PD is low. Chip bypass pin for internal midsupply reference. This point is the midpoint of a resistive voltage divider and is not 28 VMID1 intended to function as an input. It should be bypassed with a 0.1- μF capacitor. Thermal Pad PowerPAD Thermal contact for heat dissipation. The thermal pad must be connected to electrical ground. Copyright © 2009, Texas Instruments Incorporated 5 Product Folder Link(s): PGA870 |
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