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EP1AGX20C Datasheet(PDF) 10 Page - Altera Corporation |
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EP1AGX20C Datasheet(HTML) 10 Page - Altera Corporation |
10 / 34 page 1–10 Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet Functional Description Configuration Handbook (Complete Two-Volume Set) © December 2009 Altera Corporation Multiple FPGAs can be configured using a single enhanced configuration device in FPP mode. In this mode, multiple Stratix series FPGAs, APEX II FPGAs, or both, are cascaded together in a daisy chain. After the first FPGA completes configuration, its nCEO pin asserts to activate the nCE pin for the second FPGA, which prompts the second device to start capturing configuration data. In this setup, the FPGAs CONF_DONE pins are tied together, and hence all devices initialize and enter user mode simultaneously. If the enhanced configuration device or one of the FPGAs detects an error, configuration stops (and simultaneously restarts) for the whole chain because the nSTATUS pins are tied together. 1 While Altera FPGAs can be cascaded in a configuration chain, the enhanced configuration devices cannot be cascaded to configure larger devices or chains. Figure 1–2. FPP Configuration Notes to Figure 1–2: (1) The VCC should be connected to the same supply voltage as the configuration device. (2) The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is always active. This means an external pull-up resistor is not required on the nINIT_CONF / nCONFIG line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG must be pulled to VCC either directly or through a resistor. (3) The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in the Quartus® II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files. (4) For PORSEL, PGM[], and EXCLK pin connections, refer to Table 1–10. (5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15 to F-A15, C-A16 to F-A16 , and BYTE# to VCC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages: C-RP# to F-RP#, C-WE# to F-WE#, TM1 to VCC, TM0 to GND, and WP# to VCC. (6) Connect the FPGA MSEL[] input pins to select the FPP configuration mode. For details, refer to the appropriate FPGA family chapter in the Configuration Handbook. (7) To protect Intel Flash based EPC devices content, isolate the VCCW supply from VCC. For more information, refer section “Intel-Flash-Based EPC Device Protection” on page 1–15. Enhanced Configuration Device DCLK DATA[7..0] OE nCS nINIT_CONF (2) MSEL DCLK DATA[7..0] nSTATUS CONF_DONE nCONFIG VCC VCC GND GND (3) (3) nCE EXCLK Stratix Series or APEX II Device WE#C RP#C WP# PORSEL PGM[2..0] TMO WE#F RP#F A[20..0] RY/BY# CE# OE# DQ[15..0] VCC N.C. N.C. N.C. N.C. N.C. BYTE# (5) TM1 (3) (3) C-A0 (5) C-A1 (5) C-A15 (5) C-A16 (5) A0-F A1-F A15-F A16-F (1) (1) n (6) (1) nCEO N.C. (4) (4) (4) VCCW VCC (7) |
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