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PCA9555DBRG4 Datasheet(PDF) 11 Page - Texas Instruments |
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PCA9555DBRG4 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 35 page Reads 0 0 A2 A1 A0 0 1 0 0 A2 A1 A0 0 1 S 0 A A A R/W A P NA S R/W 1 MSB LSB MSB LSB Slave Address Acknowledge From Slave Command Byte Data From Upper or Lower Byte of Register Last Byte Data Acknowledge From Slave Acknowledge From Slave Slave Address Data From Lower or Upper Byte of Register First Byte Data No Acknowledge From Master Acknowledge From Master At this moment, master transmitter becomes master receiver, and slave-receiver becomes slave-transmitter. 1 2 3 4 5 6 7 8 9 S 0 1 0 0 A2 A1 A0 1 A 7 6 5 4 3 2 1 0 A I0.x 7 6 5 4 3 2 1 0 A I1.x 7 6 5 4 3 2 1 0 A I0.x 7 6 5 4 3 2 1 0 1 I1.x P R/W SCL SDA INT Read From Port 0 Data Into Port 0 Read From Port 1 Data Into Port 1 Acknowledge From Master Acknowledge From Slave Acknowledge From Master Acknowledge From Master No Acknowledge From Master tiv tir PCA9555 www.ti.com ......................................................................................................................................................... SCPS131E – AUGUST 2005 – REVISED MAY 2008 The bus master first must send the PCA9555 address with the least-significant bit set to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data from the register defined by the command byte then is sent by the PCA9555 (see Figure 8 through Figure 10). After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. Figure 8. Read From Register A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register). B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from the P port (see Figure 8 for these details). Figure 9. Read Input Port Register, Scenario 1 Copyright © 2005–2008, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): PCA9555 |
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