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PCA9555DBQR Datasheet(PDF) 10 Page - Texas Instruments |
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PCA9555DBQR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 35 page Interrupt (INT) Output Bus Transactions Writes 1 2 SCL 3 4 5 6 7 8 SDA A A A Data 0 R/W tpv 9 0 0 0 0 0 0 0 1 0.7 0.0 Data 1 1.7 1.0 A S 0 1 0 0 A2 A1 A0 0 tpv P Slave Address Command Byte Data to Port 0 Data to Port 1 Start Condition Acknowledge From Slave Write to Port Data Out from Port 1 Data Out from Port 0 Data Valid Acknowledge From Slave Acknowledge From Slave 1 2 SCL 3 4 5 6 7 8 SDA A A A Data 0 Data to Register R/W 9 0 0 0 0 0 0 1 1 MSB LSB Data 1 MSB LSB A Data to Register S 0 1 0 0 A2 A1 A0 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 P Acknowledge From Slave Acknowledge From Slave Start Condition Command Byte Slave Address Acknowledge From Slave PCA9555 SCPS131E – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting, data is read from the port that generated the interrupt or in a Stop event. Resetting occurs in the read mode at the acknowledge (ACK) bit or not acknowledge (NACK) bit after the falling edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa. INT has an open-drain structure and requires a pullup resistor to VCC. Data is exchanged between the master and the PCA9555 through write and read commands. Data is transmitted to the PCA9555 by sending the device address and setting the least-significant bit to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. The eight registers within the PCA9555 are configured to operate as four register pairs. The four pairs are input ports, output ports, polarity inversion ports, and configuration ports. After sending data to one register, the next data byte is sent to the other register in the pair (see Figure 6 and Figure 7). For example, if the first byte is sent to output port (register 3), the next byte is stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers. Figure 6. Write to Output Port Registers Figure 7. Write to Configuration Registers 10 Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): PCA9555 |
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