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SN65LVEP11DGKR Datasheet(PDF) 4 Page - Texas Instruments |
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SN65LVEP11DGKR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 12 page NECL DC CHARACTERISTICS (1) (V CC = 0.0 V; VEE = –3.8V to –2.375 V) (2) AC CHARACTERISTICS (1) (V CC = 2.375 V to 3.8 V; VEE = 0.0 V or VCC = 0.0 V; VEE = –3.8 V to SN65LVEP11 SLLS930A – NOVEMBER 2008 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com –40°C 25°C 85°C PARAMETER UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX ICC Power supply current 28 45 32 45 36 45 mA VOH Output HIGH voltage(3) –1145 –895 –1145 –1065 –895 –1145 –895 mV VOL Output LOW voltage(3) –1945 –1600 –1945 –1777 –1600 –1945 –1600 mV Input high voltage VIH –1165 –880 –1165 –880 –1165 –880 mV (Single-Ended)(4) Input low voltage VIL –1945 –1600 –1945 –1600 –1945 –1600 mV (Single-Ended)(4) VIHCM Input HIGH voltage common VEE+1.2 VEE+1.2 0.0 VEE+1.2 VEE+1.2 0.0 VEE+1.2 VEE+1.2 0.0 V R mode range (Differential)(5) IIH Input HIGH current 150 150 150 µA IIL Input LOW current (D) 0.5 0.5 0.5 µA nput LOW current (–D) –150 –150 –150 (1) The device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously (2) Input and output parameters vary 1:1 with VCC. (3) All loading with 50 Ω to VCC – 2 V. (4) Single Ended input clock pin operation is limited to VCC ≤ –3 V in NECL mode. (5) VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. –2.375 V (2) PARAMETER –40°C 25°C 85°C UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX fMAX Max switching frequency(3) (see Figure 6) 3.8 3.5 3.1 GHz tPLH/tPHL Propagation delay to output differential (CLK, Q, –Q) 200 300 200 300 200 300 ps tSKEW Device skew ( Q, –Q) 8 8 15 8 15 ps Device to Device Skew (Q, –Q) (4) 25 25 25 tJITTER Random clock jitter (RMS) ≤ 1.0 GHz 0.3 0.3 0.3 ps Random Clock Jitter (RMS) ≤ 1.5 GHz 0.2 0.2 0.2 Random Clock Jitter (RMS) ≤ 2.0 GHz 0.2 0.2 0.2 Random Clock Jitter (RMS) ≤ 2.5 GHz 0.2 0.2 0.2 Random Clock Jitter (RMS) ≤ 3.0 GHz 0.2 0.2 0.2 VPP Input swing Differential Config. 150 800 1200 150 1200 150 1200 mV tr/tf Output rise/fall times Q, –Q (20%–80%) 100 200 100 200 100 200 ps (1) The device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. (2) Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC –2 V. (3) The maximum switching frequency measured at the output amplitude of 300 mVpp. (4) Skew is measured between outputs under identical transitions 4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVEP11 |
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