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N25Q128A41TF840F Datasheet(PDF) 3 Page - Numonyx B.V

Part # N25Q128A41TF840F
Description  128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

N25Q128A41TF840F Datasheet(HTML) 3 Page - Numonyx B.V

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N25Q128 - 1.8 V
Contents
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5.2.2
Dual Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.3
Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.4
Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 28
5.2.5
Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 28
5.2.6
Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.7
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.8
HOLD (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3
Quad SPI (QIO-SPI)Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.1
Multiple Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.2
Quad Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.3
QUAD Command Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.4
Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 30
5.3.5
Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 30
5.3.6
Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.7
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.8
HOLD (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.9
VPP pin Enhanced Supply Voltage feature . . . . . . . . . . . . . . . . . . . . . . 31
6
Volatile and Non Volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1
Legacy SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1.3
BP3, BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1.4
TB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1.5
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2
Non Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.1
Dummy clock cycle NV configuration bits (NVCR bits from 15 to 12) . . 37
6.2.2
XIP NV configuration bits (NVCR bits from 11 to 9) . . . . . . . . . . . . . . . . 38
6.2.3
Output Driver Strength NV configuration bits (NVCR bits from 8 to 6) . . 38
6.2.4
Fast POR NV configuration bit (NVCR bit 5) . . . . . . . . . . . . . . . . . . . . . 38
6.2.5
Hold (Reset) disable NV configuration bit (NVCR bit 4) . . . . . . . . . . . . 38
6.2.6
Quad Input NV configuration bit (NVCR bit 3) . . . . . . . . . . . . . . . . . . . . 38
6.2.7
Dual Input NV configuration bit (NVCR bit 2) . . . . . . . . . . . . . . . . . . . . . 39
6.3
Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.1
Dummy clock cycle Volatile Configurations bits (VCR bits from 7 to 4) . 40
6.3.2
XIP Volatile Configuration bits (VCR bit 3) . . . . . . . . . . . . . . . . . . . . . . . 41
6.4
Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . 41


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