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NCP3125ADR2G Datasheet(PDF) 8 Page - ON Semiconductor

Part # NCP3125ADR2G
Description  4 A Synchronous PWM Switching Converter
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP3125ADR2G Datasheet(HTML) 8 Page - ON Semiconductor

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NCP3125
http://onsemi.com
8
COMP
0.9 V
BG
TG
Figure 17. Enable/Disable Driver State Diagram
External Soft−Start
The NCP3125 features an external soft−start function,
which reduces inrush current and overshoot of the output
voltage. Soft−start is achieved by using the internal current
source of 10.5
mA (typ), which charges the external
integrator capacitor of the OTA. Figure 18 is a typical
soft−start sequence. The sequence begins once VIN and
VBST surpass their UVLO thresholds and OCP
programming is complete. The current sourced out of the
COMP pin continually increases the voltage until regulation
is reached. Once the voltage reaches 400 mV logic is
enabled. When the voltage exceeds 900 mV, switching
begins. Current is sourced out of the COMP pin, placing the
regulator into open loop operation until 800 mV is sensed at
the FB pin. Once 800 mV is sensed at the FB pin, open loop
operation ends and closed loop operation begins. In closed
loop operation, the OTA is capable of sourcing and sinking
120
mA.
Figure 18. Soft−Start Sequence
VCC
COMP
VFB
BG
TG
BG Comparator
BG Comparator Output
Vout
UVLO POR
Delay
Current
COMP
Delay
Soft−Start Normal Operation
UVLO
0.9 V
3.85 V
4.2 V
DAC Voltage
500 mV
50 mV
Trip Set
Overcurrent Threshold Setting
NCP3125 overcurrent threshold can be set from 50 mV to
550 mV, by adding a resistor (RSET) between ISET and
GND. During a short period of time following VIN rising
over UVLO threshold, an internal 10
mA current (IOCSET) is
sourced from the ISET pin, creating a voltage drop across
RSET. The voltage drop is compared against a stepped
internal voltage ramp. Once the internal stepped voltage
reaches the RSET voltage, the value is stored internally until
power is cycled. The overall time length for the OC setting
procedure is approximately 9 ms. Connecting an RSET
resistor between ISET and GND, the programmed threshold
will be:
IOCth +
IOCSET *RSET
RDS(on)
³ 4.2 A +
10 mA*21 kW
50 mW
(eq. 1)
IOCSET = Sourced current
IOCth = Current trip threshold
RDS(on) = On resistance of the low side MOSFET
RSET = Current set resistor
The RSET values range from 5 kW to 55 kW. If RSET is not
connected, the device switches the OCP threshold to a fixed
375 mV value. An internal safety clamp on ISET is triggered
as soon as ISET voltage reaches 700 mV, enabling the
375 mV fixed threshold and ending the OCP setting period.
The current trip threshold tolerance is
±25 mV. The
accuracy is best at the highest set point (550 mV). The
accuracy will decrease as the set point decreases. MOSFET
tolerances with temperature and input voltage will vary the
over current set threshold operating point. A graph of the
typical current limit set thresholds at 4.5 V and 12 V is
shown in Figure .
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
5 6 7 8 9 1011 1213 1415 161718 1920 21
RSET (kW)
Figure 19. RSET Value for Output Current
5 V
12 V


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