52.8 µm

52.2 µm

0.0

1

2

3

4

5

6

7

8

9

10

1238.4 µm

NC

NC

(2)

(1)

NC

(3)

NC

(4)

NC

(5)

TPS40210-HT

SLVSAD8 – JUNE 2010

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

BARE DIE INFORMATION

BACKSIDE

BOND PAD

BOND PAD

DIE THICKNESS

BACKSIDE FINISH

POTENTIAL

METALLIZATION COMPOSITION

THICKNESS

15 mils.

Silicon with backgrind

GND

Al-Cu (0.5%)

0.6 µm

Table 1. Bond Pad Coordinates in Microns

DISCRIPTION

PAD NUMBER

X min

Y min

X max

Y max

RC

1

67.95

1089.45

168.75

1190.25

SS

2

28.8

714.15

129.6

814.95

DIS/EN

3

28.8

595.35

129.6

696.15

COMP

4

28.8

306.45

129.6

407.25

FB

5

28.8

115.29

129.6

216.09

GND

6

1108.62

117.45

1209.42

218.25

ISNS

7

1108.62

332.91

1209.42

433.71

GDRV

8

1108.62

451.71

1209.42

552.51

BP

9

1108.62

570.51

1209.42

671.31

VDD

10

1057.68

1114.02

1158.48

1214.82

2

Submit Documentation Feedback

Copyright © 2010, Texas Instruments Incorporated

Product Folder Link(s): TPS40210-HT