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TLK6002ZEU Datasheet(PDF) 9 Page - Texas Instruments |
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TLK6002ZEU Datasheet(HTML) 9 Page - Texas Instruments |
9 / 96 page TLK6002 www.ti.com SLLSE34 – MAY 2010 Table 2-1. Pin Description – Signal Pins (continued) Terminal Direction Type Description Signal BGA Supply Input Transceiver Power down. When this pin is held low (asserted), Channel A is placed in power down mode. When LVCMOS deasserted , Channel A operates normally. After deassertion, a software datapath reset should be issued through PD_TRXA_N T6 1.5V/1.8V the MDIO interface. VDDO3 Channel B: Serial Transmit Channel B Output. TXBP and TXBN comprise the transmit direction Channel B differential high speed serial output signal. During device reset (RESET_N asserted low) these pins are driven differential zero. Output TXBP U12 CML These CML outputs must be AC coupled. TXBN U13 AVDD During pin based power down (PD_TRXB_N asserted low), these pins are floating. During register based power down (1.15 asserted high), these pins are floating. Input Serial Receive Channel B Input. RXBP and RXBN comprise the receive direction Channel B differential high RXBP V10 CML speed serial input signal. These signals must be AC coupled. RXBN V11 AVDD Channel B Rate select pins. These pins put channel B into one of the four supported (full/half/quarter/eighth) channel operation rates, enable software control, or enable Auto Rate Sense (ARS): 000 – Full Rate mode 001 – Half Rate mode 010 – Quarter rate mode 011 – Eighth rate mode 100 – Software Selectable Rate (Recommended if ARS not used) 101 – Channel B Auto Rate Sense (ARS) Function Enabled Channel B SERDES settings are determined by Channel B ARS machine. CLK_OUT_P/N selected by CLK_OUT_SEL See Table 2-9 for additional details on CLK_OUT_P/N. 110 – Channel B Auto Rate Sense (ARS) Function Enabled Channel B SERDES settings are determined by Channel B ARS machine. CLK_OUT_P/N is not selected by CLK_OUT_SEL Input Channel A may not be simultaneously configured with RATE_A=110 U16 LVCMOS With respect to CLK_OUT_P/N, this setting has the highest priority. RATE_B[2:0] U17 1.5V/1.8V See Table 2-9 for additional details on CLK_OUT_P/N. U18 VDDO2 111 – Channel B Auto Rate Sense (ARS) Function Enabled – Slave Mode If Channel A ARS is enabled (RATE_A=101 or 110 only): Channel B SERDES settings are determined by Channel A ARS machine. CLK_OUT_P/N is not selected by CLK_OUT_SEL See Table 2-9 for additional details on CLK_OUT_P/N. If Channel A ARS is not enabled (RATE_A=000/001/010/011/111): Channel B SERDES settings are determined by Channel B MDIO registers. CLK_OUT_P/N selected by CLK_OUT_SEL See Table 2-9 for additional details on CLK_OUT_P/N. Channel A and B should not be in slave mode simultaneously. Both directions of Channel B are controlled by these input signals. The RATE_B[2] pin should be routed to an uninstalled header so that it could be driven externally in the event that device debug is required. In application mode, it should be biased with a pull up or pull down resistor, and not connected directly to a power or ground plane. Transmit Input Channel B Clock. TXCLK_B is used to sample Channel B input parallel data (TDB_[19:0]). Input HSTL This input must be synchronous (0 ppm) to the SERDES reference clock. TXCLK_B T18 1.5V/1.8V In SDR mode, this signal is equal in frequency to serial bit rate / 20. VDDQB In DDR mode, this signal is equal in frequency to serial bit rate / 40. If unused in the application, this input must be grounded. Copyright © 2010, Texas Instruments Incorporated Description 9 Submit Documentation Feedback Product Folder Link(s): TLK6002 |
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