OUT

L

H

V

PROTECT

V

–

PROTECT

V

HYS

Cell Voltage

VC1–VC2

VC2–VC3

VC3–VC4

VC4–GND

T0461-01

t

d

CD

DELAY

d

t

=

c

x

[

]

CD

d

CD

1.2 V

C

t

I

´

=

bq29440, bq2944L0

bq29449, bq2944L9

SLUSA15B – MARCH 2010 – REVISED JUNE 2010

www.ti.com

Figure 4. Timing for Overvoltage Sensing

Sizing the external capacitor is based on the desired delay time as follows:

customer should use a CCD capacitor that is 3 s / 8.5 s/µF = 0.35 µF.

The delay time is calculated as follows:

If the cell overvoltage condition is removed before the external capacitor reaches the reference voltage, the

internal current source is disabled and an internal discharge block is employed to discharge the external

capacitor down to 0 V. In this instance, the OUT pin remains in a low state.

For latched versions of the bq2944x, if an overvoltage condition has caused the OUT pin to transition to a high

state, the external capacitor remains charged even after the overvoltage condition has been removed. In this

instance, the OUT pin remains in a high state.

For non-latched versions, the OUT pin is allowed to transition back from a high to low state when the overvoltage

condition is no longer present, and the external capacitor is discharged down to 0 V.

6

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Product Folder Link(s): bq29440 bq2944L0 bq29449 bq2944L9