NB7V585M datasheet(5/8 Pages) ONSEMI

Part #	NB7V585M

Description	1.8V / 2.5V Differential 2:1 Mux Input to 1:6 CML Clock/Data Fanout Buffer/Translator

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NB7V585M

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Table 6. AC CHARACTERISTICS VCC = 1.8 V $5% or 2.5 V $5%, GND = 0 V, TA = −40°C to 85°C (Note 11)

Symbol

Characteristic

Min

Typ

Max

Unit

fMAX

Maximum Input Clock Frequency, VOUTPP w 200 mV

6.0

7.0

GHz

fDATAMAX

Maximum Operating Input Data Rate (PRBS23)

10

Gbps

VOUTPP

Output Voltage Amplitude (See Figures 4, Note 15)

fin v 4.0 GHz

fin v 6.0 GHz

250

200

400

325

mV

tPLH, tPHL Propagation Delay to Output Differential @ 1 GHz,

INx/INx to Qn/Qn

Measured at Differential Crosspoint

SEL to Qn

125

175

200

250

300

ps

tPLH TC

Propagation Delay Temperature Coefficient

100

fs/°C

tSKEW

Output − Output Skew (Within Device) (Note 12)

Device − Device Skew (tpd Max − tpdmin)

30

50

ps

tDC

Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 4.0 GHz

45

50

55

%

tJITTER

Output Random Jitter (RJ) (Note 13)

fin v 6.0 GHz

Deterministic Jitter (DJ) (Note 14)

fin v 10 Gbps

0.2

0.8

10

ps rms

ps pk−pk

VINPP

Input Voltage Swing (Differential Configuration) (Note 15)

100

1200

mV

tr, tf

Output Rise/Fall Times @ 1 GHz (20% − 80%)

Qn, Qn

50

65

ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

11. Measured using a 400 mV source, 50% duty cycle clock source. All outputs must be loaded with external 50 W to VCC. Input edge rates 40 ps

(20% − 80%).

12.Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when

the delays are measured from cross−point of the inputs to the crosspoint of the outputs.

13.Additive RMS jitter with 50% duty cycle clock signal.

14.Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.

15.Input and output voltage swing is a single−ended measurement operating in differential mode.

Figure 2. Output Voltage Amplitude (VOUTPP) vs. Input

Frequency (fin) at Ambient Temperature (Typical)

fout, CLOCK OUTPUT FREQUENCY (GHz)

Figure 3. Input Structure

50 W

VTx

VCC

INx

450

0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

400

350

300

250

200

150

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