H

V

LVL

1.2V

2.4V

Cell Voltage

OUT

CD

LVO

LVIN

(VCn - VC(n-1),

VC6 – GND)

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SLUSA00 – MARCH 2010

Figure 7. LVIN to OUT and LVO Timing

CELL CONNECTION SEQUENCE

Unused VCx cell input pins should be connected to the most positive connected cell input pin as shown in the

Battery Connection Diagrams section. VDD is connected through a resistor to the most-positive VCx pin of the

cell stack. Note that VC1 is the most-positive connection to the most-positive cell.

During pack assembly, it is recommended that the cell input pins be connected in order from lowest to highest

potential: GND, VC6, VC5, VC4, VC3, VC2, VC1.

NOTE

if a random cell connection order is used, a false overvoltage condition may be sensed

depending on the order of connection.

To prevent a fault from being detected in this scenario, the CD pin may be held low so that the fault timer is

disabled and OUT and LVO will not be activated. Alternatively, the VDD pin may be held low during cell

connection, or pulsed low after cell connection in order to reset the device.

Copyright © 2010, Texas Instruments Incorporated

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