MC74HC377A

http://onsemi.com

2

Figure 1. Logic Diagram

DATA

INPUTS

D0

11

CLOCK

D1

D2

D3

D4

D5

D6

D7

18

17

14

13

8

7

4

3

1

E

19

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

16

15

12

9

6

5

2

PIN 10 = GND

NONINVERTING

OUTPUTS

FUNCTION TABLE

Operating

Modes

Inputs

Outputs

Clock

E

Dn

Qn

Load “1”

↑

l

h

H

Load “0”

↑

l

l

L

Hold (Do Nothing)

↑

X

h

H

X

X

No Change

No Change

H = HIGH voltage level

h = HIGH voltage level one setup time prior to the LOW−to−

HIGH CP transition

L = LOW voltage level

l = LOW voltage level one setup time prior to the LOW−to−HIGH

CP transition

↑ = LOW−to−HIGH CP transition

X = Don’t Care

Design Criteria

Value

Units

Internal Gate Count*

66

ea

Internal Gate Propagation Delay

1.5

ns

Internal Gate Power Dissipation

5.0

mW

Speed Power Product

.0075

pJ

*Equivalent to a two−input NAND gate.

ORDERING INFORMATION

Device

Package

MC74HC377ADWG

SOIC−20 WIDE

(Pb−Free)

38 Units / Rail

MC74HC377ADWR2G

SOIC−20 WIDE

(Pb−Free)

1000 Tape & Reel

MC74HC377ADTG

TSSOP−20*

75 Units / Rail

MC74HC377ADTR2G

TSSOP−20*

2500 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.