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56800EFM Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc |
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56800EFM Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc |
5 / 56 page 56F805 Description 56F805 Technical Data, Rev. 16 Freescale Semiconductor 5 • Two General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with four pins • CAN 2.0 B Module with 2-pin port for transmit and receive • Two Serial Communication Interfaces, each with two pins (or four additional GPIO lines) • Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines) • 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins • Computer Operating Properly (COP) watchdog timer • Two dedicated external interrupt pins • External reset input pin for hardware reset • External reset output pin for system reset • JTAG/On-Chip Emulation (OnCE™) module for unobtrusive, processor speed-independent debugging • Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock 1.1.4 Energy Information • Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs • Uses a single 3.3V power supply • On-chip regulators for digital and analog circuitry to lower cost and reduce noise • Wait and Stop modes available 1.2 56F805 Description The 56F805 is a member of the 56800 core-based family of processors. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F805 is well-suited for many applications. The 56F805 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, and industrial control for power, lighting, and automation. The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both MCU and DSP applications. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The 56F805 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F805 also provides two external dedicated interrupt lines, and up to 32 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F805 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It also supports program execution from external memory (64K). |
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