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S9S12XEP100F1CVLR Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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S9S12XEP100F1CVLR Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
2 / 1324 page To provide the most up-to-date information, the document revision on the World Wide Web is the most current. A printed copy may be an earlier revision. To verif, refer to: http://freescale.com/ This document contains information for the complete S12XE-Family and thus includes a set of separate FTM module sections to cover the whole family. A full list of family members and options is included in the appendices. This document contains information for all constituent modules, with the exception of the S12X CPU. For S12X CPU information please refer to CPU12XV2 in the CPU12/CPU12X Reference Manual. Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 Revision History Date Revision Description May,2008 1.16 Figure B-3 Θ1 value corrected. Added LVR minimum assert level Enhanced RESET pin description. IIC register name corrected Corrected D-Flash size reference for XEG128 Changed module revision history tables to a unified format Corrected corrupted formats Jul, 2008 1.17 Added Module Run Idd Values Added 3.3V expansion bus timing Corrected NVM timing parameters Changed IIC SCL Divider note Sep, 2008 1.18 Updated NVM timing parameter section for brownout case Specified time delay from RESET to start of CPU code execution Added NVM patch Part IDs Enhanced ECT GPIO / timer function transitioning description Dec, 2008 1.19 Updated 208MAPBGA thermal parameters Revised TIM flag clearing procedure Corrected CRG register address Added maskset identifier suffix for ATMC fab Fixed typos Aug, 2009 1.20 Added 208MAPBGA disclaimer Added VREAPI to PT5. Added LVR Note to electricals. Updates to TIM/ECT/XGATE/SCI/MSCAN (see embedded rev. history) Apr, 2010 1.21 FTM section (see FTM revision history) PIM section (see PIM revision history) May, 2010 1.22 ECT and TIM sections (see ECT, TIM revision history tables) BDM Alternate clock source defined in device overview |
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