CM1293A

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Application Information

Design Considerations

In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to

minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between

example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power

supply is represented by L

V

where I

An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact

discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns.

Here d(I

combined) will lead to a 300V increment in V

Similarly for negative ESD pulses, parasitic series inductance from the V

drastically increased negative voltage on the line being protected.

The CM1293 has an integrated Zener diode between V

inductance L

possible V

recommended that a 0.22µF ceramic chip capacitor be connected between V

As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of

expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to

the V

planes and between the signal input and the ESD device to minimize stray series inductance.

Figure 3. Application of Positive ESD Pulse between Input Channel and Ground