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CAT9532YI Datasheet(PDF) 11 Page - ON Semiconductor |
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CAT9532YI Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 18 page CAT9532 External Reset Operation The CAT9532 registers and the I 2C state machine are initialized to their default state when the RESET input is held low for a minimum of tW. The external Reset timing is shown in Figure 9. Power-On Reset Operation The CAT9532 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device is in a reset state for VCC less than the internal POR threshold level (VPOR). When VCC exceeds the VPOR level, the reset state is released and the CAT9532 internal state machine and registers are initialized to their default state. Figure 8. Read Input Port Register Timing Diagram 11 0 0 A2 A1 A0 READ FROM PORT DATA INTO PORT SDA SA A DATA 1 DATA 4 Slave Address Data From Port Data From Port Start Condition R/W Acknowledge From Slave Acknowledge From Master Stop Condition tps DATA 4 DATA 2 P DATA 3 tph NA DATA 1 No Acknowledge From Master Figure 9. RESET ¯¯¯¯¯¯ Timing Diagram SDA SCL tRESET tRESET 50% 30% 50% 50% 50% tREC tW RESET LEDx LED OFF ACK OR READ CYCLE START © 2010 SCILLC. All rights reserved 11 Doc. No. MD-9001 Rev. E Characteristics subject to change without notice |
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