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CAT5401YI-00-T2 Datasheet(PDF) 8 Page - ON Semiconductor

Part # CAT5401YI-00-T2
Description  Quad Digitally Programmable Potentiometers (DPP?? with 64 Taps and SPI Interface
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT5401YI-00-T2 Datasheet(HTML) 8 Page - ON Semiconductor

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CAT5401
Doc. No. MD-2012 Rev. J
8
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
Wiper Control and Data Registers
Wiper Control Register (WCR)
The CAT5401 contains four 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of 64
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written by
the host via Write Wiper Control Register instruction; it
may be written by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction, it can be modified one step at a
time by the Increment/decrement instruction (see
Instruction section for more details). Finally, it is
loaded with the content of its data register zero (DR0)
upon power-up.
The Wiper Control Register is a volatile register that
loses its contents when the CAT5401 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Data Registers (DR)
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data
Registers is a non-volatile operation and will take a
maximum of 5ms.
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS
¯¯¯ input goes HIGH
after a write sequence is received. The status of the
internal write cycle can be monitored by issuing a
Read Status command to read the Write in Process
(WIP) bit.
Instructions
Four of the nine instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register – read the current
wiper position of the selected potentiometer in the
WCR
— Write Wiper Control Register – change current
wiper position in the WCR of the selected
potentiometer
— Read Data Register – read the contents of the
selected Data Register
— Write Data Register – write a new value to the
selected Data Register
— Read Status – Read the status of the WIP bit
which when set to "1" signifies a write cycle is in
progress.
Table 3. Instruction Set
Note: 1/0 = data is one or zero
Instruction Set
Instruction
I3
I2
I1
I0
R1
R0
WCR1/ P1
WCR0/ P0
Operation
Read Wiper Control
Register
1
0
0
1
0
0
1/0
1/0
Read the contents of the Wiper Control
Register pointed to by P1-P0
Write Wiper Control
Register
1
0
1
0
0
0
1/0
1/0
Write new value to the Wiper Control
Register pointed to by P1-P0
Read Data Register
1
0
1
1
1/0 1/0
1/0
1/0
Read the contents of the Data Register
pointed to by P1-P0 and R1-R0
Write Data Register
1
1
0
0
1/0 1/0
1/0
1/0
Write new value to the Data Register
pointed to by P1-P0 and R1-R0
XFR Data Register to
Wiper Control Register
1
1
0
1
1/0 1/0
1/0
1/0
Transfer the contents of the Data Register
pointed to by P1-P0 and R1-R0 to its
associated Wiper Control Register
XFR Wiper Control
Register to Data
Register
1
1
1
0
1/0 1/0
1/0
1/0
Transfer the contents of the Wiper Control
Register pointed to by P1-P0 to the Data
Register pointed to by R1-R0
Global XFR Data
Registers to Wiper
Control Registers
0
0
0
1
1/0 1/0
0
0
Transfer the contents of the Data Registers
pointed to by R1-R0 of all four pots to their
respective Wiper Control Registers
Global XFR Wiper
Control Registers to
Data Register
1
0
0
0
1/0 1/0
0
0
Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1-R0 of all four pots
Increment/Decrement
Wiper Control Register
0
0
1
0
0
0
1/0
1/0
Enable Increment/decrement of the Control
Latch pointed to by P1-P0
Read Status (WIP bit)
0
1
0
1
0
0
0
1
Read WIP bit to check internal write cycle
status


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