CAT5270

http://onsemi.com

5

SCL

SDA IN

SDA OUT

Figure 2. Bus Timing

Serial Bus Protocol

interface protocol:

1. Data transfer may be initiated only when the bus is

not busy.

2. During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock is high

will be interpreted as a START or STOP condition.

The device controlling the transfer is a master, typically a

processor or controller, and the device being controlled is the

slave. The master will always initiate data transfers and

provide the clock for both transmit and receive operations.

Therefore, the CAT5270 will be considered a slave device

in all applications.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of SDA

when SCL is HIGH (see Figure 3). The CAT5270 monitors

the SDA and SCL lines and will not respond until this

condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition (see Figure 3). All

operations must end with a STOP condition.

Device Addressing

The bus Master begins a transmission by sending a

START condition. The Master then sends the Slave Addres

Byte which contains the address of the particular slave

device it is requesting. The four most significant bits of the

8−bit slave address are fixed as 0101 for the CAT5270. The

next four significant bits (A3, A2, A1, A0) are the device

address bits and define which device the Master is accessing

(see Figure 5). Up to sixteen devices may be individually

are hard−wired to these pins to establish the device’s

address.

After the Master sends a START condition and the slave

address byte, the CAT5270 monitors the bus and responds

with an acknowledge (on the SDA line) when its address

matches the transmitted slave address.

Slave Address Byte

The most significant four bits of the slave address are a

device type identifier. These bits for the CAT5270 are fixed

at 0101[B] (refer to Figure 5).

The next four bits, A3 − A0, are the internal slave address

and must match the physical device address which is defined

by the state of the A3 − A0 input pins for the CAT5270 to

successfully continue the command sequence. Only the

device which slave address matches the incoming device

address sent by the master executes the instruction. The A3

− A0 inputs can be actively driven by CMOS input signals

Acknowledge

After a successful data transfer, each receiving device is

required to generate an acknowledge. The Acknowledging

device pulls down the SDA line during the ninth clock cycle,

signaling that it received the 8 bits of data (see Figure 4).

The CAT5270 responds with an acknowledge after

receiving a START condition and its slave address. If the

device has been selected along with a write operation, it

responds with an acknowledge after receiving each 8−bit

byte.

When the CAT5270 is in a READ mode it transmits 8 bits

of data, releases the SDA line, and monitors the line for an

acknowledge. Once it receives this acknowledge, the

CAT5270 will continue to transmit data. If no acknowledge

is sent by the Master, the device terminates data transmission

and waits for a STOP condition.

If the device has been selected with an IN/DEC operation

it will no longer responds with acknoleadge as the received

data it is not in a byte format.