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CAT64LC40J-GT3 Datasheet(PDF) 8 Page - ON Semiconductor |
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CAT64LC40J-GT3 Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 12 page CAT64LC40 http://onsemi.com 8 Reset The RESET pin, when set to HIGH, will reset or abort a WRITE operation. When RESET is set to HIGH while the WRITE instruction is being entered, the device will not execute the WRITE instruction and will keep DO in High−Z condition. When RESET is set to HIGH, while the device is in a clear/write cycle, the device will abort the operation and will display READY status on the RDY/BSY pin and on the DO pin if CS is low. The RESET input affects only the WRITE and WRITEALL operations. It does not reset any other operations such as READ, EWEN and EWDS. Erase/Write Enable and Disable The CAT64LC40 powers up in the erase/write disabled state. After power−up or while the device is in an erase/write disabled state, any write operation must be preceded by an execution of the EWEN instruction. Once enabled, the device will stay enabled until an EWDS has been executed or a power−down has occurred. The EWDS is used to prevent any inadvertent over−writing of the data. The EWEN and EWDS instructions have no affect on the READ operation and are not affected by the RESET input. Figure 9. EWDS Instruction Timing SK DI CS DO RESET 1 HIGH−Z HIGH RDY/BUSY 01 0 0 0 0 0 |
Similar Part No. - CAT64LC40J-GT3 |
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Similar Description - CAT64LC40J-GT3 |
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