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CAT24C208WI-GT3 Datasheet(PDF) 3 Page - ON Semiconductor

Part # CAT24C208WI-GT3
Description  8 kb Dual Port Serial EEPROM
Download  10 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT24C208WI-GT3 Datasheet(HTML) 3 Page - ON Semiconductor

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Table 5. D.C. OPERATING CHARACTERISTICS (VCC = 2.5 V to 5.5 V, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
ICC
Power Supply Current
fSCL = 100 KHz
3
mA
ISB
Standby Current (VCC = 5.0 V)
VIN = GND or either DSP or DDC VCC
50
mA
ILI
Input Leakage Current
VIN = GND to either DSP or DDC VCC
10
mA
ILO
Output Leakage Current
VOUT = GND to either DSP or DDC VCC
10
mA
VIL
Input Low Voltage
−1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VHYS
Input Hysteresis
0.05
V
VOL1
Output Low Voltage (VCC = 3 V)
IOL = 3 mA
0.4
V
VCCL1
Leakage DSP VCC to DDC VCC
±100
mA
VCCL2
Leakage DDC VCC to DSP VCC
±100
mA
Table 6. A.C. CHARACTERISTICS (VCC = 2.5 V to 5.5 V, unless otherwise specified.)
Symbol
Parameter
Min
Max
Units
READ & WRITE CYCLE LIMITS
FSCL
Clock Frequency
400
kHz
TI (Note 6)
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
tAA
SCL Low to SDA Data Out and ACK Out
0.9
ms
tBUF (Note 6)
Time the Bus Must be Free Before a New Transmission Can Start
1.3
ms
tHD:STA
Start Condition Hold Time
0.6
ms
tLOW
Clock Low Period
1.3
ms
tHIGH
Clock High Period
0.6
ms
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
0.6
ms
tHD:DAT
Data In Hold Time
0
ns
tSU:DAT
Data In Setup Time
100
ns
tR (Note 6)
SDA and SCL Rise Time
300
ns
tF (Note 6)
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Condition Setup Time
0.6
ms
tDH
Data Out Hold Time
100
ns
Table 7. POWER−UP TIMING (Notes 6 and 7)
Symbol
Parameter
Min
Typ
Max
Units
tPUR
Power−up to Read Operation
1
ms
tPUW
Power−up to Write Operation
1
ms
6. This parameter is tested initially and after a design or process change that affects the parameter.
7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Table 8. WRITE CYCLE LIMITS
Symbol
Parameter
Min
Typ
Max
Units
tWR
Write Cycle Time
5
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond
to its slave address.


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