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ADP3212A Datasheet(PDF) 9 Page - ON Semiconductor

Part # ADP3212A
Description  7-Bit, Programmable, 3-Phase, Mobile CPU Synchronous Buck Controller
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

ADP3212A Datasheet(HTML) 9 Page - ON Semiconductor

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ADP3212A, NCP3218A
http://onsemi.com
9
ELECTRICAL CHARACTERISTICS
VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,
VVID = VDAC = 1.2000 V, TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign.
Parameter
Units
Max
Typ
Min
Conditions
Symbol
HIGH−SIDE MOSFET DRIVER
Pulldown Resistance, Sinking
Current (Note 3)
BST = PVCC
0.8
2.0
W
Transition Times
trDRVH
tfDRVH
BST = PVCC, CL = 3 nF, Figure 2
BST = PVCC, CL = 3 nF, Figure 2
15
13
35
31
ns
Dead Delay Times
tpdhDRVH
BST = PVCC, Figure 2
T = −10°C to 100°C
T = −40°C to 100°C
28
32
36
50
ns
BST Quiescent Current
EN = L (Shutdown)
EN = H, no switching
1.0
200
10
mA
LOW−SIDE MOSFET DRIVER
Pullup Resistance, Sourcing
Current (Note 3)
0.88
2.8
W
Pulldown Resistance, Sinking
Current (Note 3)
0.65
1.7
W
Transition Times
trDRVL
tfDRVL
CL = 3 nF, Figure 2
CL = 3 nF, Figure 2
15
14
35
35
ns
Propagation Delay Times
tpdhDRVL
CL = 3 nF, Figure 2
T = −10°C to 100°C
T = −40°C to 100°C
11
12
30
40
ns
SW Transition Timeout
tTOSW
DRVH = L, SW = 2.5 V
T = −10°C to 100°C
T = −40°C to 100°C
85
85
250
250
300
450
ns
SW Off Threshold
VOFFSW
1.6
V
PVCC Quiescent Current
EN = L (Shutdown)
EN = H, no switching
1.0
170
10
mA
BOOTSTRAP RECTIFIER SWITCH
On Resistance (Note 3)
EN = L or EN = H and DRVL = H
5.0
7.0
12
W
1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
3. Based on bench characterization data.
4. Timing is referenced to the 90% and 10% points, unless otherwise noted.
Figure 2. Timing Diagram (Note 4)
IN
DRVH
(WITH RESPECT TO SW)
DRVL
SW
1.0 V
tfDRVH
VTH
VTH
tpdhDRVL
tpdlDRVH
trDRVL
tpdhDRVH
trDRVH
tfDRVL
tpdlDRVL


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