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TL16CP754C Datasheet(PDF) 3 Page - Texas Instruments |
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TL16CP754C Datasheet(HTML) 3 Page - Texas Instruments |
3 / 49 page TL16CP754C, TL16CM754C, TL16C754C www.ti.com SLLS644E – DECEMBER 2007 – REVISED MAY 2010 TERMINAL FUNCTIONS TERMINAL NO. I/O DESCRIPTION NAME PN PM Address bit 0 select. Internal registers address selection. Refer to Table 9 for Register A0 30 24 I Address Map. Address bit 1 select. Internal registers address selection. Refer to Table 9 for Register A1 29 23 I Address Map. Address bit 2 select. Internal registers address selection. Refer to Table 9 for Register A2 28 22 I Address Map. Carrier detect (active low). These inputs are associated with individual UART channels A CDA, CDB, 79, 23, 64, 19, I through D. A low on these pins indicates that a carrier has been detected by the modem CDC, CDD 39, 63 31, 49 for that channel. Clock select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable clock. During the reset, a logic 1 (VCC) on CLKSEL selects the divide-by-1 prescaler. A logic 0 (GND) on CLKSEL selects the divide-by-4 prescaler. The value of CLKSEL is latched into CLKSEL 26 21 I MCR[7] at the trailing edge of RESET. A logic 1 (VCC) on CLKSEL will latch a 0 into MCR[7]. A logic 0 (GND) on CLKSEL will latch a 1 into MCR[7]. MCR[7] can be changed after RESET to alter the prescaler value. Chip select A, B, C, and D (active low). These pins enable data transfers between the CSA, CSB, 9, 13, 7, 11, I user CPU and the '754C for the channel(s) addressed. Individual UART sections (A, B, CSC, CSD 49, 53 38, 42 C, D) are addressed by providing a low on the respective CSA through CSD pin. Clear to send (active low). These inputs are associated with individual UART channels A through D. A low on the CTS pins indicates the modem or data set is ready to accept CTSA, CTSB, 4, 18, 2, 16, I transmit data from the '754C. Status can be checked by reading MSR[4]. These pins CTSC, CTSD 44, 58 33, 47 only affect the transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR[7]), for hardware flow control operation. Data bus (bidirectional). These pins are the eight-bit, 3-state data bus for transferring D0–D2, 68–70, 53–60 I/O information to or from the controlling CPU. D0 is the least significant bit and the first data D3–D7 71–75 bit in a transmit or receive serial data stream. Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): TL16CP754C TL16CM754C TL16C754C |
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