NJW4351

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PIN/ CIRCUIT OPERATIONAL DEFINITION

♦ Logic Input Pins Operational Voltage Definition

♦ Logic Input Pins Timing Definition

0V

V

0.8V

5.0V

2.0V

At VDD=3.3V

L level

H level

L lebvel

H level

L level

L level input voltage

H level input voltage

0V

2.0V

0.8V

H level input voltage

L level input voltage

At VDD=3.3V

Master Pin

STEP

V

Slave Pins

t

RESET, PD

Data Setup Time and Data Hold Time are defined to positive edge of STEP.

tp

tp

HSM, DIR

tp

tp