SG2524, SG3524

REGULATING PULSEWIDTH MODULATORS

SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003

8

POST OFFICE BOX 655303

synchronous operation (continued)

If two or more SG2524 regulators are operated synchronously, all oscillator output terminals must be tied

together. The oscillator programmed for the minimum clock period is the master from which all the other

that the master output pulse, which occurs first, has a longer pulse duration and, subsequently, resets the slave

regulators.

voltage reference

The 5-V internal reference can be employed by use of an external resistor divider network to establish a

reference common-mode voltage range (1.8 V to 3.4 V) within the error amplifiers (see Figure 6), or an external

reference can be applied directly to the error amplifier. For operation from a fixed 5-V supply, the internal

configuration, however, the input voltage is limited to a maximum of 6 V.

To Negative

Output Voltage

REF OUT

5 k

Ω

R1

To Positive

Output Voltage

R2

5 k

Ω

REF OUT

+

–

+

–

5 k

Ω

5 k

Ω

R2

R1

V

O +

2.5 V R1 ) R2

R1

V

O +

2.5 V 1

* R2

R1

2.5 V

2.5 V

Figure 6. Error-Amplifier Bias Circuits

error amplifier

The error amplifier is a differential-input transconductance amplifier. The output is available for dc gain control

resistance from COMP to ground. Refer to Figure 3 for data.

compensation

COMP, as previously discussed, is made available for compensation. Since most output filters introduce one

or more additional poles at frequencies below 200 Hz, which is the pole of the uncompensated amplifier,

introduction of a zero to cancel one of the output filter poles is desirable. This can be accomplished best with

a series RC circuit from COMP to ground in the range of 50 k

Ω and 0.001 µF. Other frequencies can be canceled

by use of the formula f

≈ 1/RC.

† Throughout these discussions, references to the SG2524 apply also to the SG3524.