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SG2524DRE4 Datasheet(PDF) 8 Page - Texas Instruments |
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SG2524DRE4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 24 page SG2524, SG3524 REGULATING PULSEWIDTH MODULATORS SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION† synchronous operation (continued) If two or more SG2524 regulators are operated synchronously, all oscillator output terminals must be tied together. The oscillator programmed for the minimum clock period is the master from which all the other SG2524s operate. In this application, the CTRT values of the slaved regulators must be set for a period approximately 10% longer than that of the master regulator. In addition, CT (master) = 2 CT (slave) to ensure that the master output pulse, which occurs first, has a longer pulse duration and, subsequently, resets the slave regulators. voltage reference The 5-V internal reference can be employed by use of an external resistor divider network to establish a reference common-mode voltage range (1.8 V to 3.4 V) within the error amplifiers (see Figure 6), or an external reference can be applied directly to the error amplifier. For operation from a fixed 5-V supply, the internal reference can be bypassed by applying the input voltage to both the VCC and VREF terminals. In this configuration, however, the input voltage is limited to a maximum of 6 V. To Negative Output Voltage REF OUT 5 k Ω R1 To Positive Output Voltage R2 5 k Ω REF OUT + – + – 5 k Ω 5 k Ω R2 R1 V O + 2.5 V R1 ) R2 R1 V O + 2.5 V 1 * R2 R1 2.5 V 2.5 V Figure 6. Error-Amplifier Bias Circuits error amplifier The error amplifier is a differential-input transconductance amplifier. The output is available for dc gain control or ac phase compensation. The compensation node (COMP) is a high-impedance node (RL = 5 MΩ). The gain of the amplifier is AV = (0.002 Ω–1)RL and easily can be reduced from a nominal 10,000 by an external shunt resistance from COMP to ground. Refer to Figure 3 for data. compensation COMP, as previously discussed, is made available for compensation. Since most output filters introduce one or more additional poles at frequencies below 200 Hz, which is the pole of the uncompensated amplifier, introduction of a zero to cancel one of the output filter poles is desirable. This can be accomplished best with a series RC circuit from COMP to ground in the range of 50 k Ω and 0.001 µF. Other frequencies can be canceled by use of the formula f ≈ 1/RC. † Throughout these discussions, references to the SG2524 apply also to the SG3524. |
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