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SG2524 Datasheet(PDF) 7 Page - Texas Instruments |
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SG2524 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 24 page SG2524, SG3524 REGULATING PULSEWIDTH MODULATORS SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION† The SG2524 is a fixed-frequency pulse-width-modulation (PWM) voltage-regulator control circuit. The regulator operates at a fixed frequency that is programmed by one timing resistor, RT, and one timing capacitor, CT. RT establishes a constant charging current for CT. This results in a linear voltage ramp at CT, which is fed to the comparator, providing linear control of the output pulse duration (width) by the error amplifier. The SG2524 contains an onboard 5-V regulator that serves as a reference, as well as supplying the SG2524 internal regulator control circuitry. The internal reference voltage is divided externally by a resistor ladder network to provide a reference within the common-mode range of the error amplifier as shown in Figure 6, or an external reference can be used. The output is sensed by a second resistor divider network and the error signal is amplified. This voltage is then compared to the linear voltage ramp at CT. The resulting modulated pulse out of the high-gain comparator then is steered to the appropriate output pass transistor (Q1 or Q2) by the pulse-steering flip-flop, which is synchronously toggled by the oscillator output. The oscillator output pulse also serves as a blanking pulse to ensure both outputs are never on simultaneously during the transition times. The duration of the blanking pulse is controlled by the value of CT. The outputs may be applied in a push-pull configuration in which their frequency is one-half that of the base oscillator, or paralleled for single-ended applications in which the frequency is equal to that of the oscillator. The output of the error amplifier shares a common input to the comparator with the current-limiting and shut-down circuitry and can be overridden by signals from either of these inputs. This common point is pinned out externally via the COMP pin, which can be employed to either control the gain of the error amplifier or to compensate it. In addition, the COMP pin can be used to provide additional control to the regulator. APPLICATION INFORMATION† oscillator The oscillator controls the frequency of the SG2524 and is programmed by RT and CT as shown in Figure 4. f [ 1.30 R T C T where: RT is in kΩ CT is in µF f is in kHz Practical values of CT fall between 0.001 µF and 0.1 µF. Practical values of RT fall between 1.8 kΩ and 100 kΩ. This results in a frequency range typically from 130 Hz to 722 kHz. blanking The output pulse of the oscillator is used as a blanking pulse at the output. This pulse duration is controlled by the value of CT as shown in Figure 5. If small values of CT are required, the oscillator output pulse duration can be maintained by applying a shunt capacitance from OSC OUT to ground. synchronous operation When an external clock is desired, a clock pulse of approximately 3 V can be applied directly to the oscillator output terminal. The impedance to ground at this point is approximately 2 k Ω. In this configuration, RTCT must be selected for a clock period slightly greater than that of the external clock. † Throughout these discussions, references to the SG2524 apply also to the SG3524. |
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